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Antonio Nino Diazae6779e2017-11-06 14:49:04 +00001/*
Andre Przywara4ea3bd32019-07-09 14:32:11 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <common/desc_image_load.h>
15#include <lib/optee_utils.h>
16#include <lib/xlat_tables/xlat_mmu_helpers.h>
17#include <lib/xlat_tables/xlat_tables_defs.h>
Ying-Chun Liu (PaulLiu)34527382019-01-22 03:27:55 +080018#include <drivers/generic_delay_timer.h>
19#include <drivers/rpi3/gpio/rpi3_gpio.h>
Ying-Chun Liu (PaulLiu)de6f2f42019-01-30 04:20:38 +080020#include <drivers/rpi3/sdhost/rpi3_sdhost.h>
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000021
Andre Przywara4ea3bd32019-07-09 14:32:11 +010022#include <rpi_shared.h>
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000023
24/* Data structure which holds the extents of the trusted SRAM for BL2 */
25static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
26
Ying-Chun Liu (PaulLiu)de6f2f42019-01-30 04:20:38 +080027/* Data structure which holds the MMC info */
28static struct mmc_device_info mmc_info;
29
30static void rpi3_sdhost_setup(void)
31{
32 struct rpi3_sdhost_params params;
33
34 memset(&params, 0, sizeof(struct rpi3_sdhost_params));
35 params.reg_base = RPI3_SDHOST_BASE;
Ying-Chun Liu (PaulLiu)a5cdc082019-02-12 22:41:06 +080036 params.bus_width = MMC_BUS_WIDTH_1;
37 params.clk_rate = 50000000;
Ying-Chun Liu (PaulLiu)de6f2f42019-01-30 04:20:38 +080038 mmc_info.mmc_dev_type = MMC_IS_SD_HC;
39 rpi3_sdhost_init(&params, &mmc_info);
40}
41
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000042/*******************************************************************************
43 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
44 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
45 * Copy it to a safe location before its reclaimed by later BL2 functionality.
46 ******************************************************************************/
Antonio Nino Diaz83d8c792018-08-17 14:25:08 +010047
48void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
49 u_register_t arg2, u_register_t arg3)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000050{
Antonio Nino Diaz83d8c792018-08-17 14:25:08 +010051 meminfo_t *mem_layout = (meminfo_t *) arg1;
52
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000053 /* Initialize the console to provide early debug support */
Andre Przywara57ccecc2020-03-10 12:33:16 +000054 rpi3_console_init();
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000055
Ying-Chun Liu (PaulLiu)34527382019-01-22 03:27:55 +080056 /* Enable arch timer */
57 generic_delay_timer_init();
58
59 /* Setup GPIO driver */
Andre Przywara203e7c42020-03-11 16:10:40 +000060 rpi3_gpio_init();
Ying-Chun Liu (PaulLiu)34527382019-01-22 03:27:55 +080061
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000062 /* Setup the BL2 memory layout */
63 bl2_tzram_layout = *mem_layout;
64
Ying-Chun Liu (PaulLiu)de6f2f42019-01-30 04:20:38 +080065 /* Setup SDHost driver */
66 rpi3_sdhost_setup();
67
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000068 plat_rpi3_io_setup();
69}
70
71void bl2_platform_setup(void)
72{
73 /*
74 * This is where a TrustZone address space controller and other
Antonio Nino Diaz1f470022018-03-27 09:39:47 +010075 * security related peripherals would be configured.
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000076 */
77}
78
79/*******************************************************************************
80 * Perform the very early platform specific architectural setup here.
81 ******************************************************************************/
82void bl2_plat_arch_setup(void)
83{
84 rpi3_setup_page_tables(bl2_tzram_layout.total_base,
85 bl2_tzram_layout.total_size,
86 BL_CODE_BASE, BL_CODE_END,
87 BL_RO_DATA_BASE, BL_RO_DATA_END
88#if USE_COHERENT_MEM
89 , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
90#endif
91 );
92
93 enable_mmu_el1(0);
94}
95
96/*******************************************************************************
97 * This function can be used by the platforms to update/use image
98 * information for given `image_id`.
99 ******************************************************************************/
100int bl2_plat_handle_post_image_load(unsigned int image_id)
101{
102 int err = 0;
103 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Ying-Chun Liu (PaulLiu)d9f76e62018-06-10 02:00:27 +0800104#ifdef SPD_opteed
105 bl_mem_params_node_t *pager_mem_params = NULL;
106 bl_mem_params_node_t *paged_mem_params = NULL;
107#endif
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000108
109 assert(bl_mem_params != NULL);
110
111 switch (image_id) {
112 case BL32_IMAGE_ID:
Ying-Chun Liu (PaulLiu)d9f76e62018-06-10 02:00:27 +0800113#ifdef SPD_opteed
114 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
115 assert(pager_mem_params);
116
117 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
118 assert(paged_mem_params);
119
120 err = parse_optee_header(&bl_mem_params->ep_info,
121 &pager_mem_params->image_info,
122 &paged_mem_params->image_info);
123 if (err != 0)
124 WARN("OPTEE header parse error.\n");
125#endif
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000126 bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl32_entry();
127 break;
128
129 case BL33_IMAGE_ID:
130 /* BL33 expects to receive the primary CPU MPID (through r0) */
131 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
132 bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
Ying-Chun Liu (PaulLiu)de6f2f42019-01-30 04:20:38 +0800133
134 /* Shutting down the SDHost driver to let BL33 drives SDHost.*/
135 rpi3_sdhost_stop();
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000136 break;
137
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000138 default:
139 /* Do nothing in default case */
140 break;
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000141 }
142
143 return err;
144}