Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 7c2a3ca | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 10 | |
| 11 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 12 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
| 13 | ENTRY(bl2_entrypoint) |
| 14 | |
| 15 | MEMORY { |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 16 | #if BL2_IN_XIP_MEM |
| 17 | ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE |
| 18 | RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE |
| 19 | #else |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 20 | RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 21 | #endif |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 22 | } |
| 23 | |
Masahiro Yamada | 5289b67 | 2019-06-14 17:49:17 +0900 | [diff] [blame] | 24 | #if !BL2_IN_XIP_MEM |
| 25 | #define ROM RAM |
| 26 | #endif |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 27 | |
| 28 | SECTIONS |
| 29 | { |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 30 | #if BL2_IN_XIP_MEM |
| 31 | . = BL2_RO_BASE; |
| 32 | ASSERT(. == ALIGN(PAGE_SIZE), |
| 33 | "BL2_RO_BASE address is not aligned on a page boundary.") |
| 34 | #else |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 35 | . = BL2_BASE; |
| 36 | ASSERT(. == ALIGN(PAGE_SIZE), |
| 37 | "BL2_BASE address is not aligned on a page boundary.") |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 38 | #endif |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 39 | |
| 40 | #if SEPARATE_CODE_AND_RODATA |
| 41 | .text . : { |
| 42 | __TEXT_START__ = .; |
Roberto Vargas | 51abc34 | 2017-11-17 10:51:54 +0000 | [diff] [blame] | 43 | __TEXT_RESIDENT_START__ = .; |
| 44 | *bl2_el3_entrypoint.o(.text*) |
| 45 | *(.text.asm.*) |
| 46 | __TEXT_RESIDENT_END__ = .; |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 47 | *(.text*) |
| 48 | *(.vectors) |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 49 | . = ALIGN(PAGE_SIZE); |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 50 | __TEXT_END__ = .; |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 51 | } >ROM |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 52 | |
| 53 | .rodata . : { |
| 54 | __RODATA_START__ = .; |
| 55 | *(.rodata*) |
| 56 | |
| 57 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 58 | . = ALIGN(8); |
| 59 | __PARSER_LIB_DESCS_START__ = .; |
| 60 | KEEP(*(.img_parser_lib_descs)) |
| 61 | __PARSER_LIB_DESCS_END__ = .; |
| 62 | |
| 63 | /* |
| 64 | * Ensure 8-byte alignment for cpu_ops so that its fields are also |
| 65 | * aligned. Also ensure cpu_ops inclusion. |
| 66 | */ |
| 67 | . = ALIGN(8); |
| 68 | __CPU_OPS_START__ = .; |
| 69 | KEEP(*(cpu_ops)) |
| 70 | __CPU_OPS_END__ = .; |
| 71 | |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 72 | . = ALIGN(PAGE_SIZE); |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 73 | __RODATA_END__ = .; |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 74 | } >ROM |
Roberto Vargas | 51abc34 | 2017-11-17 10:51:54 +0000 | [diff] [blame] | 75 | |
| 76 | ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE, |
| 77 | "Resident part of BL2 has exceeded its limit.") |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 78 | #else |
| 79 | ro . : { |
| 80 | __RO_START__ = .; |
Roberto Vargas | 51abc34 | 2017-11-17 10:51:54 +0000 | [diff] [blame] | 81 | __TEXT_RESIDENT_START__ = .; |
| 82 | *bl2_el3_entrypoint.o(.text*) |
| 83 | *(.text.asm.*) |
| 84 | __TEXT_RESIDENT_END__ = .; |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 85 | *(.text*) |
| 86 | *(.rodata*) |
| 87 | |
| 88 | /* |
| 89 | * Ensure 8-byte alignment for cpu_ops so that its fields are also |
| 90 | * aligned. Also ensure cpu_ops inclusion. |
| 91 | */ |
| 92 | . = ALIGN(8); |
| 93 | __CPU_OPS_START__ = .; |
| 94 | KEEP(*(cpu_ops)) |
| 95 | __CPU_OPS_END__ = .; |
| 96 | |
| 97 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 98 | . = ALIGN(8); |
| 99 | __PARSER_LIB_DESCS_START__ = .; |
| 100 | KEEP(*(.img_parser_lib_descs)) |
| 101 | __PARSER_LIB_DESCS_END__ = .; |
| 102 | |
| 103 | *(.vectors) |
| 104 | __RO_END_UNALIGNED__ = .; |
| 105 | /* |
| 106 | * Memory page(s) mapped to this section will be marked as |
| 107 | * read-only, executable. No RW data from the next section must |
| 108 | * creep in. Ensure the rest of the current memory page is unused. |
| 109 | */ |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 110 | . = ALIGN(PAGE_SIZE); |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 111 | |
| 112 | __RO_END__ = .; |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 113 | } >ROM |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 114 | #endif |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 115 | |
| 116 | ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, |
| 117 | "cpu_ops not defined for this platform.") |
| 118 | |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 119 | #if BL2_IN_XIP_MEM |
| 120 | . = BL2_RW_BASE; |
| 121 | ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE), |
| 122 | "BL2_RW_BASE address is not aligned on a page boundary.") |
| 123 | #endif |
| 124 | |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 125 | /* |
| 126 | * Define a linker symbol to mark start of the RW memory area for this |
| 127 | * image. |
| 128 | */ |
| 129 | __RW_START__ = . ; |
| 130 | |
| 131 | /* |
| 132 | * .data must be placed at a lower address than the stacks if the stack |
| 133 | * protector is enabled. Alternatively, the .data.stack_protector_canary |
| 134 | * section can be placed independently of the main .data section. |
| 135 | */ |
| 136 | .data . : { |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 137 | __DATA_RAM_START__ = .; |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 138 | *(.data*) |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 139 | __DATA_RAM_END__ = .; |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 140 | } >RAM AT>ROM |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 141 | |
| 142 | stacks (NOLOAD) : { |
| 143 | __STACKS_START__ = .; |
| 144 | *(tzfw_normal_stacks) |
| 145 | __STACKS_END__ = .; |
| 146 | } >RAM |
| 147 | |
| 148 | /* |
| 149 | * The .bss section gets initialised to 0 at runtime. |
| 150 | * Its base address should be 16-byte aligned for better performance of the |
| 151 | * zero-initialization code. |
| 152 | */ |
| 153 | .bss : ALIGN(16) { |
| 154 | __BSS_START__ = .; |
| 155 | *(SORT_BY_ALIGNMENT(.bss*)) |
| 156 | *(COMMON) |
| 157 | __BSS_END__ = .; |
| 158 | } >RAM |
| 159 | |
| 160 | /* |
| 161 | * The xlat_table section is for full, aligned page tables (4K). |
| 162 | * Removing them from .bss avoids forcing 4K alignment on |
Antonio Nino Diaz | 7c2a3ca | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 163 | * the .bss section. The tables are initialized to zero by the translation |
| 164 | * tables library. |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 165 | */ |
| 166 | xlat_table (NOLOAD) : { |
| 167 | *(xlat_table) |
| 168 | } >RAM |
| 169 | |
| 170 | #if USE_COHERENT_MEM |
| 171 | /* |
| 172 | * The base address of the coherent memory section must be page-aligned (4K) |
| 173 | * to guarantee that the coherent data are stored on their own pages and |
| 174 | * are not mixed with normal data. This is required to set up the correct |
| 175 | * memory attributes for the coherent data page tables. |
| 176 | */ |
| 177 | coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { |
| 178 | __COHERENT_RAM_START__ = .; |
| 179 | *(tzfw_coherent_mem) |
| 180 | __COHERENT_RAM_END_UNALIGNED__ = .; |
| 181 | /* |
| 182 | * Memory page(s) mapped to this section will be marked |
| 183 | * as device memory. No other unexpected data must creep in. |
| 184 | * Ensure the rest of the current memory page is unused. |
| 185 | */ |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 186 | . = ALIGN(PAGE_SIZE); |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 187 | __COHERENT_RAM_END__ = .; |
| 188 | } >RAM |
| 189 | #endif |
| 190 | |
| 191 | /* |
| 192 | * Define a linker symbol to mark end of the RW memory area for this |
| 193 | * image. |
| 194 | */ |
| 195 | __RW_END__ = .; |
| 196 | __BL2_END__ = .; |
| 197 | |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 198 | #if BL2_IN_XIP_MEM |
| 199 | __BL2_RAM_START__ = ADDR(.data); |
| 200 | __BL2_RAM_END__ = .; |
| 201 | |
| 202 | __DATA_ROM_START__ = LOADADDR(.data); |
| 203 | __DATA_SIZE__ = SIZEOF(.data); |
| 204 | |
| 205 | /* |
| 206 | * The .data section is the last PROGBITS section so its end marks the end |
| 207 | * of BL2's RO content in XIP memory.. |
| 208 | */ |
| 209 | __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; |
| 210 | ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT, |
| 211 | "BL2's RO content has exceeded its limit.") |
| 212 | #endif |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 213 | __BSS_SIZE__ = SIZEOF(.bss); |
| 214 | |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 215 | |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 216 | #if USE_COHERENT_MEM |
| 217 | __COHERENT_RAM_UNALIGNED_SIZE__ = |
| 218 | __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; |
| 219 | #endif |
| 220 | |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 221 | #if BL2_IN_XIP_MEM |
| 222 | ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.") |
| 223 | #else |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 224 | ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 225 | #endif |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 226 | } |