| Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef RPI_HW_H |
| 8 | #define RPI_HW_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /* |
| 13 | * Peripherals |
| 14 | */ |
| 15 | |
| 16 | #define RPI_IO_BASE ULL(0xFE000000) |
| 17 | #define RPI_IO_SIZE ULL(0x02000000) |
| 18 | |
| 19 | /* |
| 20 | * ARM <-> VideoCore mailboxes |
| 21 | */ |
| 22 | #define RPI3_MBOX_OFFSET ULL(0x0000B880) |
| 23 | #define RPI3_MBOX_BASE (RPI_IO_BASE + RPI3_MBOX_OFFSET) |
| 24 | /* VideoCore -> ARM */ |
| 25 | #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) |
| 26 | #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) |
| 27 | #define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) |
| 28 | #define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) |
| 29 | #define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) |
| 30 | /* ARM -> VideoCore */ |
| 31 | #define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) |
| 32 | #define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) |
| 33 | #define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) |
| 34 | #define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) |
| 35 | #define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) |
| 36 | /* Mailbox status constants */ |
| 37 | #define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ |
| 38 | #define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ |
| 39 | |
| 40 | /* |
| 41 | * Power management, reset controller, watchdog. |
| 42 | */ |
| 43 | #define RPI3_IO_PM_OFFSET ULL(0x00100000) |
| 44 | #define RPI3_PM_BASE (RPI_IO_BASE + RPI3_IO_PM_OFFSET) |
| 45 | /* Registers on top of RPI3_PM_BASE. */ |
| 46 | #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) |
| 47 | #define RPI3_PM_RSTS_OFFSET ULL(0x00000020) |
| 48 | #define RPI3_PM_WDOG_OFFSET ULL(0x00000024) |
| 49 | /* Watchdog constants */ |
| 50 | #define RPI3_PM_PASSWORD U(0x5A000000) |
| 51 | #define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) |
| 52 | #define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) |
| 53 | /* |
| 54 | * The RSTS register is used by the VideoCore firmware when booting the |
| 55 | * Raspberry Pi to know which partition to boot from. The partition value is |
| 56 | * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware |
| 57 | * to indicate halt. |
| 58 | */ |
| 59 | #define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) |
| 60 | |
| 61 | /* |
| 62 | * Clock controller |
| 63 | */ |
| 64 | #define RPI4_IO_CLOCK_OFFSET ULL(0x00101000) |
| 65 | #define RPI4_CLOCK_BASE (RPI_IO_BASE + RPI4_IO_CLOCK_OFFSET) |
| 66 | #define RPI4_VPU_CLOCK_DIVIDER ULL(0x0000000c) |
| 67 | |
| 68 | /* |
| 69 | * Hardware random number generator. |
| 70 | */ |
| 71 | #define RPI3_IO_RNG_OFFSET ULL(0x00104000) |
| 72 | #define RPI3_RNG_BASE (RPI_IO_BASE + RPI3_IO_RNG_OFFSET) |
| 73 | #define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) |
| 74 | #define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) |
| 75 | #define RPI3_RNG_DATA_OFFSET ULL(0x00000008) |
| 76 | #define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010) |
| 77 | /* Enable/disable RNG */ |
| 78 | #define RPI3_RNG_CTRL_ENABLE U(0x1) |
| 79 | #define RPI3_RNG_CTRL_DISABLE U(0x0) |
| 80 | /* Number of currently available words */ |
| 81 | #define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24) |
| 82 | #define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF) |
| 83 | /* Value to mask interrupts caused by the RNG */ |
| 84 | #define RPI3_RNG_INT_MASK_DISABLE U(0x1) |
| 85 | |
| 86 | /* |
| 87 | * Serial port (called 'Mini UART' in the Broadcom documentation). |
| 88 | */ |
| 89 | #define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) |
| 90 | #define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET) |
| 91 | #define PLAT_RPI4_VPU_CLK_RATE ULL(1000000000) |
| 92 | |
| 93 | /* |
| 94 | * GPIO controller |
| 95 | */ |
| 96 | #define RPI3_IO_GPIO_OFFSET ULL(0x00200000) |
| 97 | #define RPI3_GPIO_BASE (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET) |
| 98 | |
| 99 | /* |
| 100 | * SDHost controller |
| 101 | */ |
| 102 | #define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) |
| 103 | #define RPI3_SDHOST_BASE (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET) |
| 104 | |
| 105 | /* |
| 106 | * GIC interrupt controller |
| 107 | */ |
| 108 | #define RPI_HAVE_GIC |
| 109 | #define RPI4_GIC_GICD_BASE ULL(0xff841000) |
| 110 | #define RPI4_GIC_GICC_BASE ULL(0xff842000) |
| 111 | |
| 112 | #define RPI4_LOCAL_CONTROL_BASE_ADDRESS ULL(0xff800000) |
| 113 | #define RPI4_LOCAL_CONTROL_PRESCALER ULL(0xff800008) |
| 114 | |
| 115 | #endif /* RPI_HW_H */ |