blob: e623e96abef34b4fcce2a0f869f28d981411e968 [file] [log] [blame]
developer1033ea12019-04-10 21:09:26 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <arch_helpers.h>
9#include <common/bl_common.h>
Julius Werner1f363212019-05-30 17:34:08 -070010#include <common/desc_image_load.h>
developer1033ea12019-04-10 21:09:26 +080011#include <plat/common/common_def.h>
12#include <drivers/console.h>
13#include <common/debug.h>
14#include <drivers/generic_delay_timer.h>
15#include <mcucfg.h>
developer3f3f1ab2019-05-02 22:26:22 +080016#include <mt_gic_v3.h>
developer1033ea12019-04-10 21:09:26 +080017#include <lib/mmio.h>
18#include <mtk_plat_common.h>
19#include <plat_debug.h>
20#include <plat_private.h>
21#include <platform_def.h>
22#include <scu.h>
23#include <drivers/ti/uart/uart_16550.h>
24
25static entry_point_info_t bl32_ep_info;
26static entry_point_info_t bl33_ep_info;
27
28static void platform_setup_cpu(void)
29{
30 mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001);
31
32 VERBOSE("addr of cci_adb400_dcm_config: 0x%x\n",
33 mmio_read_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config));
34 VERBOSE("addr of sync_dcm_config: 0x%x\n",
35 mmio_read_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config));
36
37 VERBOSE("mp0_spmc: 0x%x\n",
38 mmio_read_32((uintptr_t)&mt8183_mcucfg->mp0_cputop_spmc_ctl));
39 VERBOSE("mp1_spmc: 0x%x\n",
40 mmio_read_32((uintptr_t)&mt8183_mcucfg->mp1_cputop_spmc_ctl));
41}
42
43/*******************************************************************************
44 * Return a pointer to the 'entry_point_info' structure of the next image for
45 * the security state specified. BL33 corresponds to the non-secure image type
46 * while BL32 corresponds to the secure image type. A NULL pointer is returned
47 * if the image does not exist.
48 ******************************************************************************/
49entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
50{
51 entry_point_info_t *next_image_info;
52
53 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
Julius Werner1f363212019-05-30 17:34:08 -070054 assert(next_image_info->h.type == PARAM_EP);
developer1033ea12019-04-10 21:09:26 +080055
56 /* None of the images on this platform can have 0x0 as the entrypoint */
57 if (next_image_info->pc)
58 return next_image_info;
59 else
60 return NULL;
61}
62
63/*******************************************************************************
64 * Perform any BL31 early platform setup. Here is an opportunity to copy
65 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
66 * are lost (potentially). This needs to be done before the MMU is initialized
67 * so that the memory layout can be used while creating page tables.
68 * BL2 has flushed this information to memory, so we are guaranteed to pick up
69 * good data.
70 ******************************************************************************/
71void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
72 u_register_t arg2, u_register_t arg3)
73{
developer1033ea12019-04-10 21:09:26 +080074 static console_16550_t console;
developer3f3f1ab2019-05-02 22:26:22 +080075
developer1033ea12019-04-10 21:09:26 +080076 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
77
78 NOTICE("MT8183 bl31_setup\n");
79
Julius Werner1f363212019-05-30 17:34:08 -070080 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
developer1033ea12019-04-10 21:09:26 +080081}
82
83
84/*******************************************************************************
85 * Perform any BL31 platform setup code
86 ******************************************************************************/
87void bl31_platform_setup(void)
88{
89 platform_setup_cpu();
90 generic_delay_timer_init();
developer3f3f1ab2019-05-02 22:26:22 +080091
92 /* Initialize the GIC driver, CPU and distributor interfaces */
93 mt_gic_driver_init();
94 mt_gic_init();
developer88837432019-05-02 22:01:39 +080095
96 /* Init mcsi SF */
97 plat_mtk_cci_init_sf();
developer1033ea12019-04-10 21:09:26 +080098}
99
100/*******************************************************************************
101 * Perform the very early platform specific architectural setup here. At the
102 * moment this is only intializes the mmu in a quick and dirty way.
103 ******************************************************************************/
104void bl31_plat_arch_setup(void)
105{
developer88837432019-05-02 22:01:39 +0800106 plat_mtk_cci_init();
107 plat_mtk_cci_enable();
108
developer1033ea12019-04-10 21:09:26 +0800109 enable_scu(read_mpidr());
110
111 plat_configure_mmu_el3(BL_CODE_BASE,
112 BL_COHERENT_RAM_END - BL_CODE_BASE,
113 BL_CODE_BASE,
114 BL_CODE_END,
115 BL_COHERENT_RAM_BASE,
116 BL_COHERENT_RAM_END);
117}