Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 1 | /* |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <platform_def.h> |
| 8 | |
Max Shvetsov | 0ac3941 | 2019-11-19 11:01:26 +0000 | [diff] [blame] | 9 | #include <common/debug.h> |
Antonio Nino Diaz | 1b0c6f1 | 2019-01-23 21:08:43 +0000 | [diff] [blame] | 10 | #include <drivers/arm/css/css_mhu_doorbell.h> |
Antonio Nino Diaz | c30db5b | 2019-01-23 20:37:32 +0000 | [diff] [blame] | 11 | #include <drivers/arm/css/scmi.h> |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 12 | #include <drivers/arm/css/sds.h> |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 13 | #include <drivers/arm/gic600_multichip.h> |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 14 | #include <lib/mmio.h> |
| 15 | #include <lib/utils.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 16 | #include <plat/arm/common/plat_arm.h> |
| 17 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 18 | #include "n1sdp_def.h" |
| 19 | |
| 20 | /* |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 21 | * Platform information structure stored in SDS. |
| 22 | * This structure holds information about platform's DDR |
| 23 | * size which will be used to zero out the memory before |
| 24 | * enabling the ECC capability as well as information |
| 25 | * about multichip setup |
| 26 | * - multichip mode |
| 27 | * - slave_count |
| 28 | * - Local DDR size in GB, DDR memory in master board |
| 29 | * - Remote DDR size in GB, DDR memory in slave board |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 30 | */ |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 31 | struct n1sdp_plat_info { |
| 32 | bool multichip_mode; |
| 33 | uint8_t slave_count; |
| 34 | uint8_t local_ddr_size; |
| 35 | uint8_t remote_ddr_size; |
| 36 | } __packed; |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 37 | |
| 38 | /* |
| 39 | * BL33 image information structure stored in SDS. |
| 40 | * This structure holds the source & destination addresses and |
| 41 | * the size of the BL33 image which will be loaded by BL31. |
| 42 | */ |
| 43 | struct n1sdp_bl33_info { |
| 44 | uint32_t bl33_src_addr; |
| 45 | uint32_t bl33_dst_addr; |
| 46 | uint32_t bl33_size; |
| 47 | }; |
| 48 | |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 49 | static scmi_channel_plat_info_t n1sdp_scmi_plat_info = { |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 50 | .scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE, |
| 51 | .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, |
| 52 | .db_preserve_mask = 0xfffffffe, |
| 53 | .db_modify_mask = 0x1, |
| 54 | .ring_doorbell = &mhu_ring_doorbell |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 55 | }; |
| 56 | |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 57 | static struct gic600_multichip_data n1sdp_multichip_data __init = { |
| 58 | .rt_owner_base = PLAT_ARM_GICD_BASE, |
| 59 | .rt_owner = 0, |
| 60 | .chip_count = 1, |
| 61 | .chip_addrs = { |
| 62 | PLAT_ARM_GICD_BASE >> 16, |
| 63 | PLAT_ARM_GICD_BASE >> 16 |
| 64 | }, |
| 65 | .spi_ids = { |
Sayanta Pattanayak | fcf6852 | 2020-07-31 12:59:24 +0530 | [diff] [blame] | 66 | {32, 479}, |
| 67 | {512, 959} |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 68 | } |
| 69 | }; |
| 70 | |
| 71 | static uintptr_t n1sdp_multichip_gicr_frames[3] = { |
| 72 | PLAT_ARM_GICR_BASE, |
| 73 | PLAT_ARM_GICR_BASE + PLAT_ARM_REMOTE_CHIP_OFFSET, |
| 74 | 0 |
| 75 | }; |
| 76 | |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 77 | scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id) |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 78 | { |
| 79 | return &n1sdp_scmi_plat_info; |
| 80 | } |
Chandni Cherukuri | e4bf6a0 | 2018-11-14 13:43:59 +0530 | [diff] [blame] | 81 | |
| 82 | const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) |
| 83 | { |
| 84 | return css_scmi_override_pm_ops(ops); |
| 85 | } |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 86 | |
| 87 | /* |
| 88 | * N1SDP platform supports RDIMMs with ECC capability. To use the ECC |
| 89 | * capability, the entire DDR memory space has to be zeroed out before |
| 90 | * enabling the ECC bits in DMC620. Zeroing out several gigabytes of |
| 91 | * memory from SCP is quite time consuming so the following function |
| 92 | * is added to zero out the DDR memory from application processor which is |
| 93 | * much faster compared to SCP. BL33 binary cannot be copied to DDR memory |
| 94 | * before enabling ECC so copy_bl33 function is added to copy BL33 binary |
| 95 | * from IOFPGA-DDR3 memory to main DDR4 memory. |
| 96 | */ |
| 97 | |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 98 | void dmc_ecc_setup(uint8_t ddr_size_gb) |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 99 | { |
| 100 | uint64_t dram2_size; |
| 101 | |
| 102 | dram2_size = (ddr_size_gb * 1024UL * 1024UL * 1024UL) - |
| 103 | ARM_DRAM1_SIZE; |
| 104 | |
| 105 | INFO("Zeroing DDR memories\n"); |
| 106 | zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); |
| 107 | flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); |
| 108 | zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); |
| 109 | flush_dcache_range(ARM_DRAM2_BASE, dram2_size); |
| 110 | |
| 111 | INFO("Enabling ECC on DMCs\n"); |
Manoj Kumar | 75e4ccb | 2019-07-22 16:10:12 +0100 | [diff] [blame] | 112 | /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ |
| 113 | mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG); |
| 114 | mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG); |
| 115 | |
| 116 | /* Enable ECC in DMCs */ |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 117 | mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); |
| 118 | mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); |
Manoj Kumar | 75e4ccb | 2019-07-22 16:10:12 +0100 | [diff] [blame] | 119 | |
| 120 | /* Set DMCs to READY state */ |
| 121 | mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); |
| 122 | mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 123 | } |
| 124 | |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 125 | void remote_dmc_ecc_setup(uint8_t remote_ddr_size) |
| 126 | { |
| 127 | uint64_t remote_dram2_size; |
| 128 | |
| 129 | remote_dram2_size = (remote_ddr_size * 1024UL * 1024UL * 1024UL) - |
| 130 | N1SDP_REMOTE_DRAM1_SIZE; |
| 131 | /* multichip setup */ |
| 132 | INFO("Zeroing remote DDR memories\n"); |
| 133 | zero_normalmem((void *)N1SDP_REMOTE_DRAM1_BASE, |
| 134 | N1SDP_REMOTE_DRAM1_SIZE); |
| 135 | flush_dcache_range(N1SDP_REMOTE_DRAM1_BASE, N1SDP_REMOTE_DRAM1_SIZE); |
| 136 | zero_normalmem((void *)N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size); |
| 137 | flush_dcache_range(N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size); |
| 138 | |
| 139 | INFO("Enabling ECC on remote DMCs\n"); |
| 140 | /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ |
| 141 | mmio_write_32(N1SDP_REMOTE_DMC0_MEMC_CMD_REG, |
| 142 | N1SDP_DMC_MEMC_CMD_CONFIG); |
| 143 | mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG, |
| 144 | N1SDP_DMC_MEMC_CMD_CONFIG); |
| 145 | |
| 146 | /* Enable ECC in DMCs */ |
| 147 | mmio_setbits_32(N1SDP_REMOTE_DMC0_ERR0CTLR0_REG, |
| 148 | N1SDP_DMC_ERR0CTLR0_ECC_EN); |
| 149 | mmio_setbits_32(N1SDP_REMOTE_DMC1_ERR0CTLR0_REG, |
| 150 | N1SDP_DMC_ERR0CTLR0_ECC_EN); |
| 151 | |
| 152 | /* Set DMCs to READY state */ |
| 153 | mmio_write_32(N1SDP_REMOTE_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); |
| 154 | mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); |
| 155 | } |
| 156 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 157 | void copy_bl33(uint32_t src, uint32_t dst, uint32_t size) |
| 158 | { |
| 159 | uint32_t i; |
| 160 | |
| 161 | INFO("Copying BL33 to DDR memory\n"); |
| 162 | for (i = 0; i < size; i = i + 8) |
| 163 | mmio_write_64((dst + i), mmio_read_64(src + i)); |
| 164 | |
| 165 | for (i = 0; i < size; i = i + 8) { |
| 166 | if (mmio_read_64(src + i) != mmio_read_64(dst + i)) { |
| 167 | ERROR("Copy failed!\n"); |
| 168 | panic(); |
| 169 | } |
| 170 | } |
| 171 | } |
| 172 | |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 173 | void n1sdp_bl31_multichip_setup(void) |
| 174 | { |
| 175 | plat_arm_override_gicr_frames(n1sdp_multichip_gicr_frames); |
| 176 | gic600_multichip_init(&n1sdp_multichip_data); |
| 177 | } |
| 178 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 179 | void bl31_platform_setup(void) |
| 180 | { |
| 181 | int ret; |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 182 | struct n1sdp_plat_info plat_info; |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 183 | struct n1sdp_bl33_info bl33_info; |
| 184 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 185 | ret = sds_init(); |
| 186 | if (ret != SDS_OK) { |
| 187 | ERROR("SDS initialization failed\n"); |
| 188 | panic(); |
| 189 | } |
| 190 | |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 191 | ret = sds_struct_read(N1SDP_SDS_PLATFORM_INFO_STRUCT_ID, |
| 192 | N1SDP_SDS_PLATFORM_INFO_OFFSET, |
| 193 | &plat_info, |
| 194 | N1SDP_SDS_PLATFORM_INFO_SIZE, |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 195 | SDS_ACCESS_MODE_NON_CACHED); |
| 196 | if (ret != SDS_OK) { |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 197 | ERROR("Error getting platform info from SDS\n"); |
| 198 | panic(); |
| 199 | } |
| 200 | /* Validate plat_info SDS */ |
| 201 | if ((plat_info.local_ddr_size == 0) |
| 202 | || (plat_info.local_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) |
| 203 | || (plat_info.remote_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) |
| 204 | || (plat_info.slave_count > N1SDP_MAX_SLAVE_COUNT)) { |
| 205 | ERROR("platform info SDS is corrupted\n"); |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 206 | panic(); |
| 207 | } |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 208 | |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 209 | if (plat_info.multichip_mode) { |
| 210 | n1sdp_multichip_data.chip_count = plat_info.slave_count + 1; |
| 211 | n1sdp_bl31_multichip_setup(); |
| 212 | } |
| 213 | arm_bl31_platform_setup(); |
| 214 | |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 215 | dmc_ecc_setup(plat_info.local_ddr_size); |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 216 | |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 217 | /* Check if remote memory is present */ |
| 218 | if ((plat_info.multichip_mode) && (plat_info.remote_ddr_size != 0)) |
| 219 | remote_dmc_ecc_setup(plat_info.remote_ddr_size); |
| 220 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 221 | ret = sds_struct_read(N1SDP_SDS_BL33_INFO_STRUCT_ID, |
| 222 | N1SDP_SDS_BL33_INFO_OFFSET, |
| 223 | &bl33_info, |
| 224 | N1SDP_SDS_BL33_INFO_SIZE, |
| 225 | SDS_ACCESS_MODE_NON_CACHED); |
| 226 | if (ret != SDS_OK) { |
| 227 | ERROR("Error getting BL33 info from SDS\n"); |
| 228 | panic(); |
| 229 | } |
| 230 | copy_bl33(bl33_info.bl33_src_addr, |
| 231 | bl33_info.bl33_dst_addr, |
| 232 | bl33_info.bl33_size); |
| 233 | /* |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 234 | * Pass platform information to BL33. This method is followed as |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 235 | * currently there is no BL1/BL2 involved in boot flow of N1SDP. |
| 236 | * When TBBR is implemented for N1SDP, this method should be removed |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 237 | * and platform information should be passed to BL33 using NT_FW_CONFIG |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 238 | * passing mechanism. |
| 239 | */ |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 240 | mmio_write_32(N1SDP_PLATFORM_INFO_BASE, *(uint32_t *)&plat_info); |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 241 | } |