Blame - plat/mediatek/mt8183/include/spm.h - filogic/atf

developer

a21d47e

2019-05-02 19:29:25 +0800

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/*

*

* SPDX-License-Identifier: BSD-3-Clause

*/

#ifndef SPM_H

#define SPM_H

#define POWERON_CONFIG_EN (SPM_BASE + 0x000)

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#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)

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#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)

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#define SPM_CLK_CON (SPM_BASE + 0x00C)

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#define SPM_CLK_SETTLE (SPM_BASE + 0x010)

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#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)

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#define PCM_CON0 (SPM_BASE + 0x018)

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#define PCM_CON1 (SPM_BASE + 0x01C)

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#define PCM_IM_PTR (SPM_BASE + 0x020)

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#define PCM_IM_LEN (SPM_BASE + 0x024)

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#define PCM_REG_DATA_INI (SPM_BASE + 0x028)

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#define PCM_PWR_IO_EN (SPM_BASE + 0x02C)

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#define PCM_TIMER_VAL (SPM_BASE + 0x030)

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#define PCM_WDT_VAL (SPM_BASE + 0x034)

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#define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038)

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#define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C)

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#define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040)

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#define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044)

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#define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048)

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#define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C)

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#define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050)

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#define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054)

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#define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058)

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#define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C)

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#define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060)

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#define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064)

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#define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068)

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#define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C)

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#define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070)

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#define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074)

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#define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078)

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#define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C)

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#define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080)

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#define SPM_SWINT (SPM_BASE + 0x08C)

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#define SPM_SWINT_SET (SPM_BASE + 0x090)

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#define SPM_SWINT_CLR (SPM_BASE + 0x094)

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#define SPM_SCP_MAILBOX (SPM_BASE + 0x098)

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#define SPM_SCP_IRQ (SPM_BASE + 0x09C)

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#define SPM_TWAM_CON (SPM_BASE + 0x0A0)

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#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4)

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#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8)

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#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0)

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#define SPM_IRQ_MASK (SPM_BASE + 0x0B4)

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#define SPM_SRC_REQ (SPM_BASE + 0x0B8)

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#define SPM_SRC_MASK (SPM_BASE + 0x0BC)

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#define SPM_SRC2_MASK (SPM_BASE + 0x0C0)

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#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4)

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#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8)

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#define SCP_CLK_CON (SPM_BASE + 0x0D0)

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#define PCM_DEBUG_CON (SPM_BASE + 0x0D4)

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#define PCM_REG0_DATA (SPM_BASE + 0x100)

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#define PCM_REG1_DATA (SPM_BASE + 0x104)

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#define PCM_REG2_DATA (SPM_BASE + 0x108)

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#define PCM_REG3_DATA (SPM_BASE + 0x10C)

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#define PCM_REG4_DATA (SPM_BASE + 0x110)

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#define PCM_REG5_DATA (SPM_BASE + 0x114)

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#define PCM_REG6_DATA (SPM_BASE + 0x118)

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#define PCM_REG7_DATA (SPM_BASE + 0x11C)

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#define PCM_REG8_DATA (SPM_BASE + 0x120)

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#define PCM_REG9_DATA (SPM_BASE + 0x124)

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#define PCM_REG10_DATA (SPM_BASE + 0x128)

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#define PCM_REG11_DATA (SPM_BASE + 0x12C)

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#define PCM_REG12_DATA (SPM_BASE + 0x130)

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#define PCM_REG13_DATA (SPM_BASE + 0x134)

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#define PCM_REG14_DATA (SPM_BASE + 0x138)

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#define PCM_REG15_DATA (SPM_BASE + 0x13C)

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#define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140)

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#define PCM_REG12_EXT_DATA (SPM_BASE + 0x144)

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#define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148)

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#define PCM_EVENT_REG_STA (SPM_BASE + 0x14C)

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#define PCM_TIMER_OUT (SPM_BASE + 0x150)

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#define PCM_WDT_OUT (SPM_BASE + 0x154)

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#define SPM_IRQ_STA (SPM_BASE + 0x158)

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#define SPM_WAKEUP_STA (SPM_BASE + 0x15C)

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#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160)

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#define SPM_WAKEUP_MISC (SPM_BASE + 0x164)

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#define BUS_PROTECT_RDY (SPM_BASE + 0x168)

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#define BUS_PROTECT2_RDY (SPM_BASE + 0x16C)

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#define SUBSYS_IDLE_STA (SPM_BASE + 0x170)

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#define CPU_IDLE_STA (SPM_BASE + 0x174)

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#define PCM_FSM_STA (SPM_BASE + 0x178)

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#define PWR_STATUS (SPM_BASE + 0x180)

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#define PWR_STATUS_2ND (SPM_BASE + 0x184)

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#define CPU_PWR_STATUS (SPM_BASE + 0x188)

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#define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C)

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#define PCM_WDT_LATCH_0 (SPM_BASE + 0x190)

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#define PCM_WDT_LATCH_1 (SPM_BASE + 0x194)

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#define PCM_WDT_LATCH_2 (SPM_BASE + 0x198)

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#define DRAMC_DBG_LATCH (SPM_BASE + 0x19C)

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#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0)

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#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4)

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#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8)

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#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC)

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#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0)

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#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4)

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#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8)

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#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC)

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#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0)

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#define PCM_WDT_LATCH_3 (SPM_BASE + 0x1C4)

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#define SPM_SRC_RDY_STA (SPM_BASE + 0x1D0)

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#define MISC_STA (SPM_BASE + 0x1D4)

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#define MCU_PWR_CON (SPM_BASE + 0x200)

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#define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)

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#define MP0_CPU0_PWR_CON (SPM_BASE + 0x208)

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#define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)

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#define MP0_CPU2_PWR_CON (SPM_BASE + 0x210)

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#define MP0_CPU3_PWR_CON (SPM_BASE + 0x214)

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#define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218)

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#define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C)

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#define MP1_CPU1_PWR_CON (SPM_BASE + 0x220)

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#define MP1_CPU2_PWR_CON (SPM_BASE + 0x224)

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#define MP1_CPU3_PWR_CON (SPM_BASE + 0x228)

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#define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240)

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#define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244)

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#define MP0_CPU0_L1_PDN (SPM_BASE + 0x248)

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#define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)

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#define MP0_CPU2_L1_PDN (SPM_BASE + 0x250)

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#define MP0_CPU3_L1_PDN (SPM_BASE + 0x254)

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#define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258)

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#define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C)

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#define MP1_CPU0_L1_PDN (SPM_BASE + 0x260)

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#define MP1_CPU1_L1_PDN (SPM_BASE + 0x264)

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#define MP1_CPU2_L1_PDN (SPM_BASE + 0x268)

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#define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C)

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#define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290)

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#define DUMMY1_PWR_CON (SPM_BASE + 0x2B0)

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#define BYPASS_SPMC (SPM_BASE + 0x2B4)

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#define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8)

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#define ARMPLL_CLK_CON (SPM_BASE + 0x2BC)

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#define SPMC_IN_RET (SPM_BASE + 0x2C0)

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#define VDE_PWR_CON (SPM_BASE + 0x300)

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#define VEN_PWR_CON (SPM_BASE + 0x304)

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#define ISP_PWR_CON (SPM_BASE + 0x308)

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#define DIS_PWR_CON (SPM_BASE + 0x30C)

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#define MJC_PWR_CON (SPM_BASE + 0x310)

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#define AUDIO_PWR_CON (SPM_BASE + 0x314)

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#define IFR_PWR_CON (SPM_BASE + 0x318)

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#define DPY_PWR_CON (SPM_BASE + 0x31C)

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#define MD1_PWR_CON (SPM_BASE + 0x320)

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#define MD2_PWR_CON (SPM_BASE + 0x324)

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#define C2K_PWR_CON (SPM_BASE + 0x328)

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#define CONN_PWR_CON (SPM_BASE + 0x32C)

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#define VCOREPDN_PWR_CON (SPM_BASE + 0x330)

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#define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334)

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#define MFG_PWR_CON (SPM_BASE + 0x338)

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#define MFG_CORE0_PWR_CON (SPM_BASE + 0x33C)

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#define MFG_CORE1_PWR_CON (SPM_BASE + 0x340)

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#define CAM_PWR_CON (SPM_BASE + 0x344)

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#define SYSRAM_CON (SPM_BASE + 0x350)

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#define SYSROM_CON (SPM_BASE + 0x354)

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#define SCP_SRAM_CON (SPM_BASE + 0x358)

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#define GCPU_SRAM_CON (SPM_BASE + 0x35C)

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#define MDSYS_INTF_INFRA_PWR_CON (SPM_BASE + 0x360)

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#define MDSYS_INTF_MD1_PWR_CON (SPM_BASE + 0x364)

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#define MDSYS_INTF_C2K_PWR_CON (SPM_BASE + 0x368)

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#define BSI_TOP_SRAM_CON (SPM_BASE + 0x370)

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#define DVFSP_SRAM_CON (SPM_BASE + 0x374)

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#define MD_EXT_BUCK_ISO (SPM_BASE + 0x390)

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#define DUMMY2_PWR_CON (SPM_BASE + 0x3B0)

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#define MD1_OUTPUT_PISO_S_EN_IZ (SPM_BASE + 0x3B4)

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#define SPM_DVFS_CON (SPM_BASE + 0x400)

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#define SPM_MDBSI_CON (SPM_BASE + 0x404)

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#define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408)

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#define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C)

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#define SPM_BSI_GEN (SPM_BASE + 0x410)

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#define SPM_BSI_EN_SR (SPM_BASE + 0x414)

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#define SPM_BSI_CLK_SR (SPM_BASE + 0x418)

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#define SPM_BSI_D0_SR (SPM_BASE + 0x41C)

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#define SPM_BSI_D1_SR (SPM_BASE + 0x420)

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#define SPM_BSI_D2_SR (SPM_BASE + 0x424)

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#define SPM_AP_SEMA (SPM_BASE + 0x428)

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#define SPM_SPM_SEMA (SPM_BASE + 0x42C)

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#define AP2MD_CROSS_TRIGGER (SPM_BASE + 0x430)

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#define AP_MDSRC_REQ (SPM_BASE + 0x434)

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#define SPM2MD_DVFS_CON (SPM_BASE + 0x438)

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#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C)

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#define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440)

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#define DPY_LP_CON (SPM_BASE + 0x444)

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#define CPU_DVFS_REQ (SPM_BASE + 0x448)

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#define SPM_PLL_CON (SPM_BASE + 0x44C)

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#define SPM_EMI_BW_MODE (SPM_BASE + 0x450)

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#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454)

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#define ULPOSC_CON (SPM_BASE + 0x458)

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#define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460)

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#define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464)

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#define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470)

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#define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474)

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#define SPM_SEMA_M0 (SPM_BASE + 0x480)

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#define SPM_SEMA_M1 (SPM_BASE + 0x484)

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#define SPM_SEMA_M2 (SPM_BASE + 0x488)

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#define SPM_SEMA_M3 (SPM_BASE + 0x48C)

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#define SPM_SEMA_M4 (SPM_BASE + 0x490)

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#define SPM_SEMA_M5 (SPM_BASE + 0x494)

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#define SPM_SEMA_M6 (SPM_BASE + 0x498)

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#define SPM_SEMA_M7 (SPM_BASE + 0x49C)

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#define SPM_SEMA_M8 (SPM_BASE + 0x4A0)

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#define SPM_SEMA_M9 (SPM_BASE + 0x4A4)

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#define SRAM_DREQ_ACK (SPM_BASE + 0x4AC)

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#define SRAM_DREQ_CON (SPM_BASE + 0x4B0)

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#define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4)

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#define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8)

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#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500)

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#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504)

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#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508)

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#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C)

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#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510)

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#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514)

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#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518)

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#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C)

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#define MP0_CPU0_WFI_EN (SPM_BASE + 0x530)

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#define MP0_CPU1_WFI_EN (SPM_BASE + 0x534)

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#define MP0_CPU2_WFI_EN (SPM_BASE + 0x538)

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#define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C)

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#define MP1_CPU0_WFI_EN (SPM_BASE + 0x540)

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#define MP1_CPU1_WFI_EN (SPM_BASE + 0x544)

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#define MP1_CPU2_WFI_EN (SPM_BASE + 0x548)

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#define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C)

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#define CPU_PTPOD2_CON (SPM_BASE + 0x560)

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#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570)

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#define ROOT_CORE_ADDR (SPM_BASE + 0x574)

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#define CPU_SPARE_CON (SPM_BASE + 0x580)

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#define CPU_SPARE_CON_SET (SPM_BASE + 0x584)

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#define CPU_SPARE_CON_CLR (SPM_BASE + 0x588)

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#define SPM_SW_FLAG (SPM_BASE + 0x600)

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#define SPM_SW_DEBUG (SPM_BASE + 0x604)

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#define SPM_SW_RSV_0 (SPM_BASE + 0x608)

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#define SPM_SW_RSV_1 (SPM_BASE + 0x60C)

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#define SPM_SW_RSV_2 (SPM_BASE + 0x610)

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#define SPM_SW_RSV_3 (SPM_BASE + 0x614)

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#define SPM_SW_RSV_4 (SPM_BASE + 0x618)

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#define SPM_SW_RSV_5 (SPM_BASE + 0x61C)

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#define SPM_RSV_CON (SPM_BASE + 0x620)

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#define SPM_RSV_STA (SPM_BASE + 0x624)

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#define SPM_PASR_DPD_0 (SPM_BASE + 0x630)

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#define SPM_PASR_DPD_1 (SPM_BASE + 0x634)

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#define SPM_PASR_DPD_2 (SPM_BASE + 0x638)

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#define SPM_PASR_DPD_3 (SPM_BASE + 0x63C)

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#define SPM_SPARE_CON (SPM_BASE + 0x640)

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#define SPM_SPARE_CON_SET (SPM_BASE + 0x644)

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#define SPM_SPARE_CON_CLR (SPM_BASE + 0x648)

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#define SPM_SW_RSV_6 (SPM_BASE + 0x64C)

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#define SPM_SW_RSV_7 (SPM_BASE + 0x650)

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#define SPM_SW_RSV_8 (SPM_BASE + 0x654)

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#define SPM_SW_RSV_9 (SPM_BASE + 0x658)

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#define SPM_SW_RSV_10 (SPM_BASE + 0x65C)

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#define SPM_SW_RSV_11 (SPM_BASE + 0x660)

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#define SPM_SW_RSV_12 (SPM_BASE + 0x664)

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#define SPM_SW_RSV_13 (SPM_BASE + 0x668)

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#define SPM_SW_RSV_14 (SPM_BASE + 0x66C)

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#define SPM_SW_RSV_15 (SPM_BASE + 0x670)

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#define SPM_SW_RSV_16 (SPM_BASE + 0x674)

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#define SPM_SW_RSV_17 (SPM_BASE + 0x678)

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#define SPM_SW_RSV_18 (SPM_BASE + 0x67C)

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#define SPM_SW_RSV_19 (SPM_BASE + 0x680)

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#define SW_CRTL_EVENT (SPM_BASE + 0x690)

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#define MP1_CPU3_PWR_STA_MASK (1U << 19)

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#define MP1_CPU2_PWR_STA_MASK (1U << 18)

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#define MP1_CPU1_PWR_STA_MASK (1U << 17)

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#define MP1_CPU0_PWR_STA_MASK (1U << 16)

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#define MP1_CPUTOP_PWR_STA_MASK (1U << 15)

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#define MCU_PWR_STA_MASK (1U << 14)

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#define MP0_CPU3_PWR_STA_MASK (1U << 12)

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#define MP0_CPU2_PWR_STA_MASK (1U << 11)

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#define MP0_CPU1_PWR_STA_MASK (1U << 10)

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#define MP0_CPU0_PWR_STA_MASK (1U << 9)

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#define MP0_CPUTOP_PWR_STA_MASK (1U << 8)

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#define MP1_CPU3_STANDBYWFI (1U << 17)

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#define MP1_CPU2_STANDBYWFI (1U << 16)

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#define MP1_CPU1_STANDBYWFI (1U << 15)

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#define MP1_CPU0_STANDBYWFI (1U << 14)

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#define MP0_CPU3_STANDBYWFI (1U << 13)

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#define MP0_CPU2_STANDBYWFI (1U << 12)

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#define MP0_CPU1_STANDBYWFI (1U << 11)

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#define MP0_CPU0_STANDBYWFI (1U << 10)

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#define MP0_SPMC_SRAM_DORMANT_EN (1<<0)

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#define MP1_SPMC_SRAM_DORMANT_EN (1<<1)

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#define MP2_SPMC_SRAM_DORMANT_EN (1<<2)

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/* POWERON_CONFIG_EN (0x10006000+0x000) */

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#define BCLK_CG_EN_LSB (1U << 0) /* 1b */

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#define PROJECT_CODE_LSB (1U << 16) /* 16b */

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/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */

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#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */

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/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */

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#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */

302

303

/* SPM_CLK_CON (0x10006000+0x00C) */

304

#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */

305

#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */

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#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */

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#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */

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#define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */

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#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */

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#define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */

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#define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */

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#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */

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#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */

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#define SRCLKEN1_EN_LSB (1U << 14) /* 1b */

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#define SCP_DCM_EN_LSB (1U << 15) /* 1b */

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#define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */

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#define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */

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/* SPM_CLK_SETTLE (0x10006000+0x010) */

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#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */

321

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/* SPM_AP_STANDBY_CON (0x10006000+0x014) */

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#define WFI_OP_LSB (1U << 0) /* 1b */

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#define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */

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#define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */

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#define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */

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#define MM_MASK_B_LSB (1U << 16) /* 2b */

328

#define MD_DDR_EN_DBC_EN_LSB (1U << 18) /* 1b */

329

#define MD_MASK_B_LSB (1U << 19) /* 2b */

330

#define SCP_MASK_B_LSB (1U << 21) /* 1b */

331

#define LTE_MASK_B_LSB (1U << 22) /* 1b */

332

#define SRCCLKENI_MASK_B_LSB (1U << 23) /* 1b */

333

#define MD_APSRC_1_SEL_LSB (1U << 24) /* 1b */

334

#define MD_APSRC_0_SEL_LSB (1U << 25) /* 1b */

335

#define CONN_MASK_B_LSB (1U << 26) /* 1b */

336

#define CONN_APSRC_SEL_LSB (1U << 27) /* 1b */

337

338

/* PCM_CON0 (0x10006000+0x018) */

339

#define PCM_KICK_L_LSB (1U << 0) /* 1b */

340

#define IM_KICK_L_LSB (1U << 1) /* 1b */

341

#define PCM_CK_EN_LSB (1U << 2) /* 1b */

342

#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */

343

#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */

344

#define PCM_SW_RESET_LSB (1U << 15) /* 1b */

345

#define PROJECT_CODE_LSB (1U << 16) /* 16b */

346

347

/* PCM_CON1 (0x10006000+0x01C) */

348

#define IM_SLAVE_LSB (1U << 0) /* 1b */

349

#define IM_SLEEP_LSB (1U << 1) /* 1b */

350

#define MIF_APBEN_LSB (1U << 3) /* 1b */

351

#define IM_PDN_LSB (1U << 4) /* 1b */

352

#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */

353

#define IM_NONRP_EN_LSB (1U << 6) /* 1b */

354

#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */

355

#define PCM_WDT_EN_LSB (1U << 8) /* 1b */

356

#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */

357

#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */

358

#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */

359

#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */

360

#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */

361

#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */

362

#define PROJECT_CODE_LSB (1U << 16) /* 16b */

363

364

/* PCM_IM_PTR (0x10006000+0x020) */

365

#define PCM_IM_PTR_LSB (1U << 0) /* 32b */

366

367

/* PCM_IM_LEN (0x10006000+0x024) */

368

#define PCM_IM_LEN_LSB (1U << 0) /* 13b */

369

370

/* PCM_REG_DATA_INI (0x10006000+0x028) */

371

#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */

372

373

/* PCM_PWR_IO_EN (0x10006000+0x02C) */

374

#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */

375

#define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */

376

377

/* PCM_TIMER_VAL (0x10006000+0x030) */

378

#define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */

379

380

/* PCM_WDT_VAL (0x10006000+0x034) */

381

#define PCM_WDT_VAL_LSB (1U << 0) /* 32b */

382

383

/* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */

384

#define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */

385

#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */

386

#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */

387

388

/* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */

389

#define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */

390

391

/* PCM_EVENT_VECTOR0 (0x10006000+0x040) */

392

#define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */

393

#define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */

394

#define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */

395

#define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */

396

397

/* PCM_EVENT_VECTOR1 (0x10006000+0x044) */

398

#define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */

399

#define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */

400

#define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */

401

#define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */

402

403

/* PCM_EVENT_VECTOR2 (0x10006000+0x048) */

404

#define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */

405

#define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */

406

#define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */

407

#define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */

408

409

/* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */

410

#define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */

411

#define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */

412

#define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */

413

#define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */

414

415

/* PCM_EVENT_VECTOR4 (0x10006000+0x050) */

416

#define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */

417

#define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */

418

#define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */

419

#define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */

420

421

/* PCM_EVENT_VECTOR5 (0x10006000+0x054) */

422

#define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */

423

#define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */

424

#define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */

425

#define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */

426

427

/* PCM_EVENT_VECTOR6 (0x10006000+0x058) */

428

#define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */

429

#define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */

430

#define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */

431

#define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */

432

433

/* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */

434

#define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */

435

#define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */

436

#define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */

437

#define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */

438

439

/* PCM_EVENT_VECTOR8 (0x10006000+0x060) */

440

#define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */

441

#define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */

442

#define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */

443

#define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */

444

445

/* PCM_EVENT_VECTOR9 (0x10006000+0x064) */

446

#define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */

447

#define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */

448

#define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */

449

#define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */

450

451

/* PCM_EVENT_VECTOR10 (0x10006000+0x068) */

452

#define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */

453

#define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */

454

#define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */

455

#define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */

456

457

/* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */

458

#define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */

459

#define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */

460

#define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */

461

#define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */

462

463

/* PCM_EVENT_VECTOR12 (0x10006000+0x070) */

464

#define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */

465

#define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */

466

#define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */

467

#define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */

468

469

/* PCM_EVENT_VECTOR13 (0x10006000+0x074) */

470

#define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */

471

#define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */

472

#define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */

473

#define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */

474

475

/* PCM_EVENT_VECTOR14 (0x10006000+0x078) */

476

#define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */

477

#define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */

478

#define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */

479

#define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */

480

481

/* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */

482

#define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */

483

#define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */

484

#define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */

485

#define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */

486

487

/* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */

488

#define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */

489

490

/* SPM_SWINT (0x10006000+0x08C) */

491

#define SPM_SWINT_LSB (1U << 0) /* 10b */

492

493

/* SPM_SWINT_SET (0x10006000+0x090) */

494

#define SPM_SWINT_SET_LSB (1U << 0) /* 10b */

495

496

/* SPM_SWINT_CLR (0x10006000+0x094) */

497

#define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */

498

499

/* SPM_SCP_MAILBOX (0x10006000+0x098) */

500

#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */

501

502

/* SPM_SCP_IRQ (0x10006000+0x09C) */

503

#define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */

504

#define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */

505

506

/* SPM_TWAM_CON (0x10006000+0x0A0) */

507

#define TWAM_ENABLE_LSB (1U << 0) /* 1b */

508

#define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */

509

#define TWAM_SW_RST_LSB (1U << 2) /* 1b */

510

#define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */

511

#define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */

512

#define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */

513

#define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */

514

#define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */

515

#define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */

516

#define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */

517

#define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */

518

519

/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */

520

#define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */

521

522

/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */

523

#define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */

524

525

/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */

526

#define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */

527

528

/* SPM_IRQ_MASK (0x10006000+0x0B4) */

529

#define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */

530

#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */

531

#define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */

532

533

/* SPM_SRC_REQ (0x10006000+0x0B8) */

534

#define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */

535

#define SPM_F26M_REQ_LSB (1U << 1) /* 1b */

536

#define SPM_LTE_REQ_LSB (1U << 2) /* 1b */

537

#define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */

538

#define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */

539

#define SPM_DVFS_REQ_LSB (1U << 5) /* 1b */

540

#define SPM_DVFS_FORCE_DOWN_LSB (1U << 6) /* 1b */

541

#define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */

542

#define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */

543

#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */

544

545

/* SPM_SRC_MASK (0x10006000+0x0BC) */

546

#define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */

547

#define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */

548

#define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */

549

#define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */

550

#define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */

551

#define CCIFMD_MD1_EVENT_MASK_B_LSB (1U << 5) /* 1b */

552

#define CCIFMD_MD2_EVENT_MASK_B_LSB (1U << 6) /* 1b */

553

#define DSI0_VSYNC_MASK_B_LSB (1U << 7) /* 1b */

554

#define DSI1_VSYNC_MASK_B_LSB (1U << 8) /* 1b */

555

#define DPI_VSYNC_MASK_B_LSB (1U << 9) /* 1b */

556

#define ISP0_VSYNC_MASK_B_LSB (1U << 10) /* 1b */

557

#define ISP1_VSYNC_MASK_B_LSB (1U << 11) /* 1b */

558

#define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 12) /* 1b */

559

#define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 13) /* 1b */

560

#define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 14) /* 1b */

561

#define MD32_SRCCLKENA_INFRA_MASK_B_LSB (1U << 15) /* 1b */

562

#define SRCCLKENI_INFRA_MASK_B_LSB (1U << 16) /* 1b */

563

#define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 17) /* 1b */

564

#define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 18) /* 1b */

565

#define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 19) /* 1b */

566

#define MD32_APSRCREQ_INFRA_MASK_B_LSB (1U << 20) /* 1b */

567

#define MD_DDR_EN_0_MASK_B_LSB (1U << 21) /* 1b */

568

#define MD_DDR_EN_1_MASK_B_LSB (1U << 22) /* 1b */

569

#define MD_VRF18_REQ_0_MASK_B_LSB (1U << 23) /* 1b */

570

#define MD_VRF18_REQ_1_MASK_B_LSB (1U << 24) /* 1b */

571

#define MD1_DVFS_REQ_MASK_LSB (1U << 25) /* 2b */

572

#define CPU_DVFS_REQ_MASK_LSB (1U << 27) /* 1b */

573

#define EMI_BW_DVFS_REQ_MASK_LSB (1U << 28) /* 1b */

574

#define MD_SRCCLKENA_0_DVFS_REQ_MASK_B_LSB (1U << 29) /* 1b */

575

#define MD_SRCCLKENA_1_DVFS_REQ_MASK_B_LSB (1U << 30) /* 1b */

576

#define CONN_SRCCLKENA_DVFS_REQ_MASK_B_LSB (1U << 31) /* 1b */

577

578

/* SPM_SRC2_MASK (0x10006000+0x0C0) */

579

#define DVFS_HALT_MASK_B_LSB (1U << 0) /* 5b */

580

#define VDEC_REQ_MASK_B_LSB (1U << 6) /* 1b */

581

#define GCE_REQ_MASK_B_LSB (1U << 7) /* 1b */

582

#define CPU_MD_DVFS_REQ_MERGE_MASK_B_LSB (1U << 8) /* 1b */

583

#define MD_DDR_EN_DVFS_HALT_MASK_B_LSB (1U << 9) /* 2b */

584

#define DSI0_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 11) /* 1b */

585

#define DSI1_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 12) /* 1b */

586

#define DPI_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 13) /* 1b */

587

#define ISP0_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 14) /* 1b */

588

#define ISP1_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 15) /* 1b */

589

#define CONN_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */

590

#define DISP_REQ_MASK_B_LSB (1U << 17) /* 1b */

591

#define DISP1_REQ_MASK_B_LSB (1U << 18) /* 1b */

592

#define MFG_REQ_MASK_B_LSB (1U << 19) /* 1b */

593

#define C2K_PS_RCCIF_WAKE_MASK_B_LSB (1U << 20) /* 1b */

594

#define C2K_L1_RCCIF_WAKE_MASK_B_LSB (1U << 21) /* 1b */

595

#define PS_C2K_RCCIF_WAKE_MASK_B_LSB (1U << 22) /* 1b */

596

#define L1_C2K_RCCIF_WAKE_MASK_B_LSB (1U << 23) /* 1b */

597

#define SDIO_ON_DVFS_REQ_MASK_B_LSB (1U << 24) /* 1b */

598

#define EMI_BOOST_DVFS_REQ_MASK_B_LSB (1U << 25) /* 1b */

599

#define CPU_MD_EMI_DVFS_REQ_PROT_DIS_LSB (1U << 26) /* 1b */

600

#define DRAMC_SPCMD_APSRC_REQ_MASK_B_LSB (1U << 27) /* 1b */

601

602

/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */

603

#define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */

604

605

/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */

606

#define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */

607

608

/* SCP_CLK_CON (0x10006000+0x0D0) */

609

#define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */

610

611

/* PCM_DEBUG_CON (0x10006000+0x0D4) */

612

#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */

613

614

/* PCM_REG0_DATA (0x10006000+0x100) */

615

#define PCM_REG0_DATA_LSB (1U << 0) /* 32b */

616

617

/* PCM_REG1_DATA (0x10006000+0x104) */

618

#define PCM_REG1_DATA_LSB (1U << 0) /* 32b */

619

620

/* PCM_REG2_DATA (0x10006000+0x108) */

621

#define PCM_REG2_DATA_LSB (1U << 0) /* 32b */

622

623

/* PCM_REG3_DATA (0x10006000+0x10C) */

624

#define PCM_REG3_DATA_LSB (1U << 0) /* 32b */

625

626

/* PCM_REG4_DATA (0x10006000+0x110) */

627

#define PCM_REG4_DATA_LSB (1U << 0) /* 32b */

628

629

/* PCM_REG5_DATA (0x10006000+0x114) */

630

#define PCM_REG5_DATA_LSB (1U << 0) /* 32b */

631

632

/* PCM_REG6_DATA (0x10006000+0x118) */

633

#define PCM_REG6_DATA_LSB (1U << 0) /* 32b */

634

635

/* PCM_REG7_DATA (0x10006000+0x11C) */

636

#define PCM_REG7_DATA_LSB (1U << 0) /* 32b */

637

638

/* PCM_REG8_DATA (0x10006000+0x120) */

639

#define PCM_REG8_DATA_LSB (1U << 0) /* 32b */

640

641

/* PCM_REG9_DATA (0x10006000+0x124) */

642

#define PCM_REG9_DATA_LSB (1U << 0) /* 32b */

643

644

/* PCM_REG10_DATA (0x10006000+0x128) */

645

#define PCM_REG10_DATA_LSB (1U << 0) /* 32b */

646

647

/* PCM_REG11_DATA (0x10006000+0x12C) */

648

#define PCM_REG11_DATA_LSB (1U << 0) /* 32b */

649

650

/* PCM_REG12_DATA (0x10006000+0x130) */

651

#define PCM_REG12_DATA_LSB (1U << 0) /* 32b */

652

653

/* PCM_REG13_DATA (0x10006000+0x134) */

654

#define PCM_REG13_DATA_LSB (1U << 0) /* 32b */

655

656

/* PCM_REG14_DATA (0x10006000+0x138) */

657

#define PCM_REG14_DATA_LSB (1U << 0) /* 32b */

658

659

/* PCM_REG15_DATA (0x10006000+0x13C) */

660

#define PCM_REG15_DATA_LSB (1U << 0) /* 32b */

661

662

/* PCM_REG12_MASK_B_STA (0x10006000+0x140) */

663

#define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */

664

665

/* PCM_REG12_EXT_DATA (0x10006000+0x144) */

666

#define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */

667

668

/* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */

669

#define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */

670

671

/* PCM_EVENT_REG_STA (0x10006000+0x14C) */

672

#define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */

673

674

/* PCM_TIMER_OUT (0x10006000+0x150) */

675

#define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */

676

677

/* PCM_WDT_OUT (0x10006000+0x154) */

678

#define PCM_WDT_OUT_LSB (1U << 0) /* 32b */

679

680

/* SPM_IRQ_STA (0x10006000+0x158) */

681

#define TWAM_IRQ_LSB (1U << 2) /* 1b */

682

#define PCM_IRQ_LSB (1U << 3) /* 1b */

683

#define SPM_IRQ_SWINT_LSB (1U << 4) /* 10b */

684

685

/* SPM_WAKEUP_STA (0x10006000+0x15C) */

686

#define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */

687

688

/* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */

689

#define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */

690

691

/* SPM_WAKEUP_MISC (0x10006000+0x164) */

692

#define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */

693

#define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */

694

#define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */

695

696

/* BUS_PROTECT_RDY (0x10006000+0x168) */

697

#define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */

698

699

/* BUS_PROTECT2_RDY (0x10006000+0x16C) */

700

#define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */

701

702

/* SUBSYS_IDLE_STA (0x10006000+0x170) */

703

#define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */

704

705

/* CPU_IDLE_STA (0x10006000+0x174) */

706

#define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */

707

#define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */

708

#define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */

709

#define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */

710

#define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */

711

#define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */

712

#define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */

713

#define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */

714

#define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */

715

#define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */

716

#define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */

717

#define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */

718

#define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */

719

#define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */

720

#define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */

721

#define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */

722

#define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */

723

#define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */

724

#define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */

725

#define MCUSYS_IDLE_LSB (1U << 23) /* 1b */

726

727

/* PCM_FSM_STA (0x10006000+0x178) */

728

#define EXEC_INST_OP_LSB (1U << 0) /* 4b */

729

#define PC_STATE_LSB (1U << 4) /* 3b */

730

#define IM_STATE_LSB (1U << 7) /* 3b */

731

#define MASTER_STATE_LSB (1U << 10) /* 5b */

732

#define EVENT_FSM_LSB (1U << 15) /* 3b */

733

#define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */

734

#define PCM_KICK_LSB (1U << 21) /* 1b */

735

#define IM_KICK_LSB (1U << 22) /* 1b */

736

#define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */

737

#define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */

738

739

/* PWR_STATUS (0x10006000+0x180) */

740

#define PWR_STATUS_LSB (1U << 0) /* 32b */

741

742

/* PWR_STATUS_2ND (0x10006000+0x184) */

743

#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */

744

745

/* CPU_PWR_STATUS (0x10006000+0x188) */

746

#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */

747

748

/* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */

749

#define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */

750

751

/* PCM_WDT_LATCH_0 (0x10006000+0x190) */

752

#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */

753

754

/* PCM_WDT_LATCH_1 (0x10006000+0x194) */

755

#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */

756

757

/* PCM_WDT_LATCH_2 (0x10006000+0x198) */

758

#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */

759

760

/* DRAMC_DBG_LATCH (0x10006000+0x19C) */

761

#define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */

762

763

/* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */

764

#define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */

765

766

/* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */

767

#define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */

768

769

/* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */

770

#define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */

771

772

/* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */

773

#define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */

774

775

/* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */

776

#define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */

777

778

/* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */

779

#define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */

780

781

/* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */

782

#define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */

783

784

/* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */

785

#define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */

786

787

/* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */

788

#define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */

789

790

/* PCM_WDT_LATCH_3 (0x10006000+0x1C4) */

791

#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */

792

793

/* SPM_SRC_RDY_STA (0x10006000+0x1D0) */

794

#define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */

795

#define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */

796

797

/* MISC_STA (0x10006000+0x1D4) */

798

#define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */

799

800

/* MCU_PWR_CON (0x10006000+0x200) */

801

#define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */

802

#define MCU_PWR_ISO_LSB (1U << 1) /* 1b */

803

#define MCU_PWR_ON_LSB (1U << 2) /* 1b */

804

#define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */

805

#define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

806

#define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */

807

#define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

808

#define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

809

#define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */

810

#define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

811

#define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

812

#define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

813

814

/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */

815

#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */

816

#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */

817

#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */

818

#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */

819

#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

820

#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */

821

#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

822

#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

823

#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */

824

#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

825

#define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

826

#define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

827

828

/* MP0_CPU0_PWR_CON (0x10006000+0x208) */

829

#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */

830

#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */

831

#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */

832

#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */

833

#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

834

#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */

835

#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

836

#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

837

#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */

838

#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

839

#define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

840

#define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

841

842

/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */

843

#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */

844

#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */

845

#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */

846

#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */

847

#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

848

#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */

849

#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

850

#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

851

#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */

852

#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

853

#define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

854

#define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

855

856

/* MP0_CPU2_PWR_CON (0x10006000+0x210) */

857

#define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */

858

#define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */

859

#define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */

860

#define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */

861

#define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

862

#define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */

863

#define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

864

#define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

865

#define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */

866

#define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

867

#define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

868

#define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

869

870

/* MP0_CPU3_PWR_CON (0x10006000+0x214) */

871

#define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */

872

#define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */

873

#define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */

874

#define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */

875

#define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

876

#define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */

877

#define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

878

#define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

879

#define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */

880

#define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

881

#define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

882

#define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

883

884

/* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */

885

#define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */

886

#define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */

887

#define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */

888

#define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */

889

#define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

890

#define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */

891

#define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

892

#define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

893

#define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */

894

#define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

895

#define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

896

#define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

897

898

/* MP1_CPU0_PWR_CON (0x10006000+0x21C) */

899

#define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */

900

#define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */

901

#define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */

902

#define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */

903

#define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

904

#define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */

905

#define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

906

#define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

907

#define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */

908

#define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

909

#define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

910

#define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

911

912

/* MP1_CPU1_PWR_CON (0x10006000+0x220) */

913

#define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */

914

#define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */

915

#define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */

916

#define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */

917

#define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

918

#define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */

919

#define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

920

#define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

921

#define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */

922

#define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

923

#define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

924

#define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

925

926

/* MP1_CPU2_PWR_CON (0x10006000+0x224) */

927

#define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */

928

#define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */

929

#define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */

930

#define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */

931

#define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

932

#define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */

933

#define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

934

#define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

935

#define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */

936

#define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

937

#define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

938

#define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

939

940

/* MP1_CPU3_PWR_CON (0x10006000+0x228) */

941

#define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */

942

#define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */

943

#define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */

944

#define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */

945

#define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

946

#define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */

947

#define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */

948

#define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */

949

#define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */

950

#define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */

951

#define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */

952

#define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */

953

954

/* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */

955

#define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */

956

#define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */

957

958

/* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */

959

#define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */

960

#define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */

961

962

/* MP0_CPU0_L1_PDN (0x10006000+0x248) */

963

#define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */

964

#define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */

965

966

/* MP0_CPU1_L1_PDN (0x10006000+0x24C) */

967

#define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */

968

#define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */

969

970

/* MP0_CPU2_L1_PDN (0x10006000+0x250) */

971

#define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */

972

#define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */

973

974

/* MP0_CPU3_L1_PDN (0x10006000+0x254) */

975

#define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */

976

#define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */

977

978

/* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */

979

#define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */

980

#define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */

981

982

/* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */

983

#define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */

984

#define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */

985

986

/* MP1_CPU0_L1_PDN (0x10006000+0x260) */

987

#define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */

988

#define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */

989

990

/* MP1_CPU1_L1_PDN (0x10006000+0x264) */

991

#define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */

992

#define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */

993

994

/* MP1_CPU2_L1_PDN (0x10006000+0x268) */

995

#define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */

996

#define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */

997

998

/* MP1_CPU3_L1_PDN (0x10006000+0x26C) */

999

#define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */

1000

#define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */

1001

1002

/* CPU_EXT_BUCK_ISO (0x10006000+0x290) */

1003

#define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */

1004

#define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */

1005

1006

/* DUMMY1_PWR_CON (0x10006000+0x2B0) */

1007

#define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */

1008

#define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */

1009

#define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */

1010

#define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1011

#define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1012

1013

/* BYPASS_SPMC (0x10006000+0x2B4) */

1014

#define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */

1015

1016

/* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */

1017

#define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */

1018

#define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */

1019

1020

/* ARMPLL_CLK_CON (0x10006000+0x2BC) */

1021

#define MUXSEL_SC_CCIPLL_LSB (1U << 0) /* 1b */

1022

#define MUXSEL_SC_ARMPLL1_LSB (1U << 1) /* 1b */

1023

#define MUXSEL_SC_ARMPLL2_LSB (1U << 2) /* 1b */

1024

#define REG_SC_ARM_CLK_OFF_LSB (1U << 8) /* 4b */

1025

#define REG_SC_ARMPLL_OFF_LSB (1U << 12) /* 4b */

1026

#define REG_SC_ARMPLLOUT_OFF_LSB (1U << 16) /* 4b */

1027

#define REG_SC_FHC_PAUSE_LSB (1U << 20) /* 4b */

1028

#define REG_SC_ARMPLL_S_OFF_LSB (1U << 24) /* 4b */

1029

1030

/* SPMC_IN_RET (0x10006000+0x2C0) */

1031

#define SPMC_STATUS_LSB (1U << 0) /* 8b */

1032

1033

/* VDE_PWR_CON (0x10006000+0x300) */

1034

#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */

1035

#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */

1036

#define VDE_PWR_ON_LSB (1U << 2) /* 1b */

1037

#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1038

#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1039

#define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */

1040

#define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1041

1042

/* VEN_PWR_CON (0x10006000+0x304) */

1043

#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */

1044

#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */

1045

#define VEN_PWR_ON_LSB (1U << 2) /* 1b */

1046

#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1047

#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1048

#define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */

1049

#define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1050

1051

/* ISP_PWR_CON (0x10006000+0x308) */

1052

#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */

1053

#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */

1054

#define ISP_PWR_ON_LSB (1U << 2) /* 1b */

1055

#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1056

#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1057

#define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */

1058

#define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1059

1060

/* DIS_PWR_CON (0x10006000+0x30C) */

1061

#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */

1062

#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */

1063

#define DIS_PWR_ON_LSB (1U << 2) /* 1b */

1064

#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1065

#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1066

#define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */

1067

#define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1068

1069

/* MJC_PWR_CON (0x10006000+0x310) */

1070

#define MJC_PWR_RST_B_LSB (1U << 0) /* 1b */

1071

#define MJC_PWR_ISO_LSB (1U << 1) /* 1b */

1072

#define MJC_PWR_ON_LSB (1U << 2) /* 1b */

1073

#define MJC_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1074

#define MJC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1075

#define MJC_SRAM_PDN_LSB (1U << 8) /* 4b */

1076

#define MJC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1077

1078

/* AUDIO_PWR_CON (0x10006000+0x314) */

1079

#define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */

1080

#define AUD_PWR_ISO_LSB (1U << 1) /* 1b */

1081

#define AUD_PWR_ON_LSB (1U << 2) /* 1b */

1082

#define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1083

#define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1084

#define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */

1085

#define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1086

1087

/* IFR_PWR_CON (0x10006000+0x318) */

1088

#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */

1089

#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */

1090

#define IFR_PWR_ON_LSB (1U << 2) /* 1b */

1091

#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1092

#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1093

#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */

1094

#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1095

1096

/* DPY_PWR_CON (0x10006000+0x31C) */

1097

#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */

1098

#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */

1099

#define DPY_PWR_ON_LSB (1U << 2) /* 1b */

1100

#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1101

#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1102

#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */

1103

#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1104

1105

/* MD1_PWR_CON (0x10006000+0x320) */

1106

#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */

1107

#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */

1108

#define MD1_PWR_ON_LSB (1U << 2) /* 1b */

1109

#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1110

#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1111

#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */

1112

1113

/* MD2_PWR_CON (0x10006000+0x324) */

1114

#define MD2_PWR_RST_B_LSB (1U << 0) /* 1b */

1115

#define MD2_PWR_ISO_LSB (1U << 1) /* 1b */

1116

#define MD2_PWR_ON_LSB (1U << 2) /* 1b */

1117

#define MD2_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1118

#define MD2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1119

#define MD2_SRAM_PDN_LSB (1U << 8) /* 1b */

1120

1121

/* C2K_PWR_CON (0x10006000+0x328) */

1122

#define C2K_PWR_RST_B_LSB (1U << 0) /* 1b */

1123

#define C2K_PWR_ISO_LSB (1U << 1) /* 1b */

1124

#define C2K_PWR_ON_LSB (1U << 2) /* 1b */

1125

#define C2K_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1126

#define C2K_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1127

1128

/* CONN_PWR_CON (0x10006000+0x32C) */

1129

#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */

1130

#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */

1131

#define CONN_PWR_ON_LSB (1U << 2) /* 1b */

1132

#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1133

#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1134

#define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */

1135

#define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */

1136

1137

/* VCOREPDN_PWR_CON (0x10006000+0x330) */

1138

#define VCOREPDN_PWR_RST_B_LSB (1U << 0) /* 1b */

1139

#define VCOREPDN_PWR_ISO_LSB (1U << 1) /* 1b */

1140

#define VCOREPDN_PWR_ON_LSB (1U << 2) /* 1b */

1141

#define VCOREPDN_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1142

#define VCOREPDN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1143

1144

/* MFG_ASYNC_PWR_CON (0x10006000+0x334) */

1145

#define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */

1146

#define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */

1147

#define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */

1148

#define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1149

#define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1150

#define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */

1151

#define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1152

1153

/* MFG_PWR_CON (0x10006000+0x338) */

1154

#define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */

1155

#define MFG_PWR_ISO_LSB (1U << 1) /* 1b */

1156

#define MFG_PWR_ON_LSB (1U << 2) /* 1b */

1157

#define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1158

#define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1159

#define MFG_SRAM_PDN_LSB (1U << 8) /* 6b */

1160

#define MFG_SRAM_PDN_ACK_LSB (1U << 16) /* 6b */

1161

1162

/* MFG_CORE0_PWR_CON (0x10006000+0x33C) */

1163

#define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */

1164

#define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */

1165

#define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */

1166

#define MFG_CORE0_ON_2ND_LSB (1U << 3) /* 1b */

1167

#define MFG_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */

1168

#define MFG_CORE0_SRAM_PDN_LSB (1U << 5) /* 1b */

1169

#define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */

1170

1171

/* MFG_CORE1_PWR_CON (0x10006000+0x340) */

1172

#define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */

1173

#define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */

1174

#define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */

1175

#define MFG_CORE1_ON_2ND_LSB (1U << 3) /* 1b */

1176

#define MFG_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */

1177

#define MFG_CORE1_SRAM_PDN_LSB (1U << 5) /* 1b */

1178

#define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */

1179

1180

/* CAM_PWR_CON (0x10006000+0x344) */

1181

#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */

1182

#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */

1183

#define CAM_PWR_ON_LSB (1U << 2) /* 1b */

1184

#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1185

#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1186

#define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */

1187

#define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1188

1189

/* SYSRAM_CON (0x10006000+0x350) */

1190

#define IFR_SRAMROM_SRAM_PDN_LSB (1U << 0) /* 8b */

1191

#define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 8) /* 8b */

1192

#define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 16) /* 8b */

1193

#define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 24) /* 8b */

1194

1195

/* SYSROM_CON (0x10006000+0x354) */

1196

#define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */

1197

1198

/* SCP_SRAM_CON (0x10006000+0x358) */

1199

#define SCP_SRAM_PDN_LSB (1U << 0) /* 1b */

1200

#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */

1201

#define SCP_SRAM_ISOINT_B_LSB (1U << 8) /* 1b */

1202

1203

/* GCPU_SRAM_CON (0x10006000+0x35C) */

1204

#define GCPU_SRAM_PDN_LSB (1U << 0) /* 4b */

1205

#define GCPU_SRAM_CKISO_LSB (1U << 4) /* 4b */

1206

#define GCPU_SRAM_SLEEP_B_LSB (1U << 8) /* 4b */

1207

#define GCPU_SRAM_ISOINT_B_LSB (1U << 12) /* 4b */

1208

1209

/* MDSYS_INTF_INFRA_PWR_CON (0x10006000+0x360) */

1210

#define MDSYS_INTF_INFRA_PWR_RST_B_LSB (1U << 0) /* 1b */

1211

#define MDSYS_INTF_INFRA_PWR_ISO_LSB (1U << 1) /* 1b */

1212

#define MDSYS_INTF_INFRA_PWR_ON_LSB (1U << 2) /* 1b */

1213

#define MDSYS_INTF_INFRA_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1214

#define MDSYS_INTF_INFRA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1215

1216

/* MDSYS_INTF_MD1_PWR_CON (0x10006000+0x364) */

1217

#define MDSYS_INTF_MD1_PWR_RST_B_LSB (1U << 0) /* 1b */

1218

#define MDSYS_INTF_MD1_PWR_ISO_LSB (1U << 1) /* 1b */

1219

#define MDSYS_INTF_MD1_PWR_ON_LSB (1U << 2) /* 1b */

1220

#define MDSYS_INTF_MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1221

#define MDSYS_INTF_MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1222

1223

/* MDSYS_INTF_C2K_PWR_CON (0x10006000+0x368) */

1224

#define MDSYS_INTF_C2K_PWR_RST_B_LSB (1U << 0) /* 1b */

1225

#define MDSYS_INTF_C2K_PWR_ISO_LSB (1U << 1) /* 1b */

1226

#define MDSYS_INTF_C2K_PWR_ON_LSB (1U << 2) /* 1b */

1227

#define MDSYS_INTF_C2K_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1228

#define MDSYS_INTF_C2K_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1229

1230

/* BSI_TOP_SRAM_CON (0x10006000+0x370) */

1231

#define BSI_TOP_SRAM_PDN_LSB (1U << 0) /* 7b */

1232

#define BSI_TOP_SRAM_DSLP_LSB (1U << 7) /* 7b */

1233

#define BSI_TOP_SRAM_SLEEP_B_LSB (1U << 14) /* 7b */

1234

#define BSI_TOP_SRAM_ISOINT_B_LSB (1U << 21) /* 7b */

1235

#define BSI_TOP_SRAM_ISO_EN_LSB (1U << 28) /* 2b */

1236

1237

/* DVFSP_SRAM_CON (0x10006000+0x374) */

1238

#define DVFSP_SRAM_PDN_LSB (1U << 0) /* 2b */

1239

#define DVFSP_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */

1240

#define DVFSP_SRAM_ISOINT_B_LSB (1U << 8) /* 2b */

1241

1242

/* MD_EXT_BUCK_ISO (0x10006000+0x390) */

1243

#define MD_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */

1244

1245

/* DUMMY2_PWR_CON (0x10006000+0x3B0) */

1246

#define DUMMY2_PWR_RST_B_LSB (1U << 0) /* 1b */

1247

#define DUMMY2_PWR_ISO_LSB (1U << 1) /* 1b */

1248

#define DUMMY2_PWR_ON_LSB (1U << 2) /* 1b */

1249

#define DUMMY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */

1250

#define DUMMY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */

1251

#define DUMMY2_SRAM_PDN_LSB (1U << 8) /* 4b */

1252

#define DUMMY2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */

1253

1254

/* MD1_OUTPUT_PISO_S_EN_IZ (0x10006000+0x3B4) */

1255

#define MD1_OUTPUT_PISO_S_EN_IZ_LSB (1U << 0) /* 1b */

1256

1257

/* SPM_DVFS_CON (0x10006000+0x400) */

1258

#define SPM_DVFS_CON_LSB (1U << 0) /* 4b */

1259

#define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */

1260

1261

/* SPM_MDBSI_CON (0x10006000+0x404) */

1262

#define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */

1263

1264

/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */

1265

#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */

1266

1267

/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */

1268

#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */

1269

1270

/* SPM_BSI_GEN (0x10006000+0x410) */

1271

#define SPM_BSI_START_LSB (1U << 0) /* 1b */

1272

1273

/* SPM_BSI_EN_SR (0x10006000+0x414) */

1274

#define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */

1275

1276

/* SPM_BSI_CLK_SR (0x10006000+0x418) */

1277

#define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */

1278

1279

/* SPM_BSI_D0_SR (0x10006000+0x41C) */

1280

#define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */

1281

1282

/* SPM_BSI_D1_SR (0x10006000+0x420) */

1283

#define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */

1284

1285

/* SPM_BSI_D2_SR (0x10006000+0x424) */

1286

#define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */

1287

1288

/* SPM_AP_SEMA (0x10006000+0x428) */

1289

#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */

1290

1291

/* SPM_SPM_SEMA (0x10006000+0x42C) */

1292

#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */

1293

1294

/* AP2MD_CROSS_TRIGGER (0x10006000+0x430) */

1295

#define AP2MD_CROSS_TRIGGER_REQ_LSB (1U << 0) /* 1b */

1296

#define AP2MD_CROSS_TRIGGER_ACK_LSB (1U << 1) /* 1b */

1297

1298

/* AP_MDSRC_REQ (0x10006000+0x434) */

1299

#define AP_MD1SRC_REQ_LSB (1U << 0) /* 1b */

1300

#define AP_MD2SRC_REQ_LSB (1U << 1) /* 1b */

1301

#define AP_MD1SRC_ACK_LSB (1U << 4) /* 1b */

1302

#define AP_MD2SRC_ACK_LSB (1U << 5) /* 1b */

1303

1304

/* SPM2MD_DVFS_CON (0x10006000+0x438) */

1305

#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 16b */

1306

1307

/* MD2SPM_DVFS_CON (0x10006000+0x43C) */

1308

#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 16b */

1309

1310

/* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */

1311

#define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */

1312

#define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */

1313

#define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */

1314

#define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */

1315

#define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */

1316

#define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */

1317

#define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */

1318

1319

/* DPY_LP_CON (0x10006000+0x444) */

1320

#define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */

1321

1322

/* CPU_DVFS_REQ (0x10006000+0x448) */

1323

#define CPU_DVFS_REQ_LSB (1U << 0) /* 16b */

1324

#define DVFS_HALT_LSB (1U << 16) /* 1b */

1325

#define MD_DVFS_ERROR_STATUS_LSB (1U << 17) /* 1b */

1326

1327

/* SPM_PLL_CON (0x10006000+0x44C) */

1328

#define SC_MPLLOUT_OFF_LSB (1U << 0) /* 1b */

1329

#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */

1330

#define SC_MPLL_OFF_LSB (1U << 4) /* 1b */

1331

#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */

1332

#define SC_MPLL_S_OFF_LSB (1U << 8) /* 1b */

1333

#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */

1334

#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */

1335

#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */

1336

1337

/* SPM_EMI_BW_MODE (0x10006000+0x450) */

1338

#define EMI_BW_MODE_LSB (1U << 0) /* 1b */

1339

#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */

1340

1341

/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */

1342

#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */

1343

1344

/* ULPOSC_CON (0x10006000+0x458) */

1345

#define ULPOSC_EN_LSB (1U << 0) /* 1b */

1346

#define ULPOSC_RST_LSB (1U << 1) /* 1b */

1347

#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */

1348

1349

/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */

1350

#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */

1351

#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */

1352

#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */

1353

#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */

1354

#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */

1355

#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */

1356

#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */

1357

#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */

1358

#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */

1359

#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */

1360

#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */

1361

#define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */

1362

#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */

1363

#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */

1364

#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */

1365

#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */

1366

1367

/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */

1368

#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */

1369

#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */

1370

#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */

1371

#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */

1372

#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */

1373

#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */

1374

#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */

1375

#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */

1376

#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */

1377

#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */

1378

#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */

1379

#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */

1380

#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */

1381

#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */

1382

#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */

1383

1384

/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */

1385

#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */

1386

#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */

1387

#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */

1388

#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */

1389

#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */

1390

#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */

1391

#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */

1392

1393

/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */

1394

#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */

1395

#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */

1396

#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */

1397

#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */

1398

#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */

1399

#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */

1400

#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */

1401

#define SPM2MM_ULTRAREQ_LSB (1U << 8) /* 1b */

1402

#define SPM2MD_ULTRAREQ_LSB (1U << 9) /* 1b */

1403

#define SPM2MM_ULTRAACK_D2T_LSB (1U << 30) /* 1b */

1404

#define SPM2MD_ULTRAACK_D2T_LSB (1U << 31) /* 1b */

1405

1406

/* SPM_SEMA_M0 (0x10006000+0x480) */

1407

#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */

1408

1409

/* SPM_SEMA_M1 (0x10006000+0x484) */

1410

#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */

1411

1412

/* SPM_SEMA_M2 (0x10006000+0x488) */

1413

#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */

1414

1415

/* SPM_SEMA_M3 (0x10006000+0x48C) */

1416

#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */

1417

1418

/* SPM_SEMA_M4 (0x10006000+0x490) */

1419

#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */

1420

1421

/* SPM_SEMA_M5 (0x10006000+0x494) */

1422

#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */

1423

1424

/* SPM_SEMA_M6 (0x10006000+0x498) */

1425

#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */

1426

1427

/* SPM_SEMA_M7 (0x10006000+0x49C) */

1428

#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */

1429

1430

/* SPM_SEMA_M8 (0x10006000+0x4A0) */

1431

#define SPM_SEMA_M8_LSB (1U << 0) /* 8b */

1432

1433

/* SPM_SEMA_M9 (0x10006000+0x4A4) */

1434

#define SPM_SEMA_M9_LSB (1U << 0) /* 8b */

1435

1436

/* SRAM_DREQ_ACK (0x10006000+0x4AC) */

1437

#define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */

1438

1439

/* SRAM_DREQ_CON (0x10006000+0x4B0) */

1440

#define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */

1441

1442

/* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */

1443

#define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */

1444

1445

/* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */

1446

#define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */

1447

1448

/* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */

1449

#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */

1450

#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */

1451

1452

/* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */

1453

#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */

1454

#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */

1455

1456

/* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */

1457

#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */

1458

#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */

1459

1460

/* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */

1461

#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */

1462

#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */

1463

1464

/* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */

1465

#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */

1466

#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */

1467

1468

/* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */

1469

#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */

1470

#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */

1471

1472

/* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */

1473

#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */

1474

#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */

1475

1476

/* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */

1477

#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */

1478

#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */

1479

1480

/* MP0_CPU0_WFI_EN (0x10006000+0x530) */

1481

#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */

1482

1483

/* MP0_CPU1_WFI_EN (0x10006000+0x534) */

1484

#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */

1485

1486

/* MP0_CPU2_WFI_EN (0x10006000+0x538) */

1487

#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */

1488

1489

/* MP0_CPU3_WFI_EN (0x10006000+0x53C) */

1490

#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */

1491

1492

/* MP1_CPU0_WFI_EN (0x10006000+0x540) */

1493

#define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */

1494

1495

/* MP1_CPU1_WFI_EN (0x10006000+0x544) */

1496

#define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */

1497

1498

/* MP1_CPU2_WFI_EN (0x10006000+0x548) */

1499

#define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */

1500

1501

/* MP1_CPU3_WFI_EN (0x10006000+0x54C) */

1502

#define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */

1503

1504

/* CPU_PTPOD2_CON (0x10006000+0x560) */

1505

#define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */

1506

#define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */

1507

#define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */

1508

#define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */

1509

#define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */

1510

#define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */

1511

1512

/* ROOT_CPUTOP_ADDR (0x10006000+0x570) */

1513

#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */

1514

1515

/* ROOT_CORE_ADDR (0x10006000+0x574) */

1516

#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */

1517

1518

/* CPU_SPARE_CON (0x10006000+0x580) */

1519

#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */

1520

1521

/* CPU_SPARE_CON_SET (0x10006000+0x584) */

1522

#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */

1523

1524

/* CPU_SPARE_CON_CLR (0x10006000+0x588) */

1525

#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */

1526

1527

/* SPM_SW_FLAG (0x10006000+0x600) */

1528

#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */

1529

1530

/* SPM_SW_DEBUG (0x10006000+0x604) */

1531

#define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */

1532

1533

/* SPM_SW_RSV_0 (0x10006000+0x608) */

1534

#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */

1535

1536

/* SPM_SW_RSV_1 (0x10006000+0x60C) */

1537

#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */

1538

1539

/* SPM_SW_RSV_2 (0x10006000+0x610) */

1540

#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */

1541

1542

/* SPM_SW_RSV_3 (0x10006000+0x614) */

1543

#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */

1544

1545

/* SPM_SW_RSV_4 (0x10006000+0x618) */

1546

#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */

1547

1548

/* SPM_SW_RSV_5 (0x10006000+0x61C) */

1549

#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */

1550

1551

/* SPM_RSV_CON (0x10006000+0x620) */

1552

#define SPM_RSV_CON_LSB (1U << 0) /* 16b */

1553

1554

/* SPM_RSV_STA (0x10006000+0x624) */

1555

#define SPM_RSV_STA_LSB (1U << 0) /* 16b */

1556

1557

/* SPM_PASR_DPD_0 (0x10006000+0x630) */

1558

#define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */

1559

1560

/* SPM_PASR_DPD_1 (0x10006000+0x634) */

1561

#define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */

1562

1563

/* SPM_PASR_DPD_2 (0x10006000+0x638) */

1564

#define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */

1565

1566

/* SPM_PASR_DPD_3 (0x10006000+0x63C) */

1567

#define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */

1568

1569

/* SPM_SPARE_CON (0x10006000+0x640) */

1570

#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */

1571

1572

/* SPM_SPARE_CON_SET (0x10006000+0x644) */

1573

#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */

1574

1575

/* SPM_SPARE_CON_CLR (0x10006000+0x648) */

1576

#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */

1577

1578

/* SPM_SW_RSV_6 (0x10006000+0x64C) */

1579

#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */

1580

1581

/* SPM_SW_RSV_7 (0x10006000+0x650) */

1582

#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */

1583

1584

/* SPM_SW_RSV_8 (0x10006000+0x654) */

1585

#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */

1586

1587

/* SPM_SW_RSV_9 (0x10006000+0x658) */

1588

#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */

1589

1590

/* SPM_SW_RSV_10 (0x10006000+0x65C) */

1591

#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */

1592

1593

/* SPM_SW_RSV_11 (0x10006000+0x660) */

1594

#define SPM_SW_RSV_11_LSB (1U << 0) /* 32b */

1595

1596

/* SPM_SW_RSV_12 (0x10006000+0x664) */

1597

#define SPM_SW_RSV_12_LSB (1U << 0) /* 32b */

1598

1599

/* SPM_SW_RSV_13 (0x10006000+0x668) */

1600

#define SPM_SW_RSV_13_LSB (1U << 0) /* 32b */

1601

1602

/* SPM_SW_RSV_14 (0x10006000+0x66C) */

1603

#define SPM_SW_RSV_14_LSB (1U << 0) /* 32b */

1604

1605

/* SPM_SW_RSV_15 (0x10006000+0x670) */

1606

#define SPM_SW_RSV_15_LSB (1U << 0) /* 32b */

1607

1608

/* SPM_SW_RSV_16 (0x10006000+0x674) */

1609

#define SPM_SW_RSV_16_LSB (1U << 0) /* 32b */

1610

1611

/* SPM_SW_RSV_17 (0x10006000+0x678) */

1612

#define SPM_SW_RSV_17_LSB (1U << 0) /* 32b */

1613

1614

/* SPM_SW_RSV_18 (0x10006000+0x67C) */

1615

#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */

1616

1617

/* SPM_SW_RSV_19 (0x10006000+0x680) */

1618

#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */

1619

1620

/* SW_CRTL_EVENT (0x10006000+0x690) */

1621

#define SW_CRTL_EVENT_ON_LSB (1U << 0) /* 1b */

1622

1623

#define SPM_PROJECT_CODE 0xb16

1624

1625

#define SPM_REGWR_EN (1U << 0)

1626

#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)

1627

1628

#define SPM_CPU_PDN_DIS (1U << 0)

1629

#define SPM_INFRA_PDN_DIS (1U << 1)

1630

#define SPM_DDRPHY_PDN_DIS (1U << 2)

1631

#define SPM_DUALVCORE_PDN_DIS (1U << 3)

1632

#define SPM_PASR_DIS (1U << 4)

1633

#define SPM_DPD_DIS (1U << 5)

1634

#define SPM_SODI_DIS (1U << 6)

1635

#define SPM_MEMPLL_RESET (1U << 7)

1636

#define SPM_MAINPLL_PDN_DIS (1U << 8)

1637

#define SPM_CPU_DVS_DIS (1U << 9)

1638

#define SPM_CPU_DORMANT (1U << 10)

1639

#define SPM_EXT_VSEL_GPIO103 (1U << 11)

1640

#define SPM_DDR_HIGH_SPEED (1U << 12)

1641

#define SPM_OPT (1U << 13)

1642

1643

#define POWER_ON_VAL1_DEF 0x15820

1644

#define PCM_FSM_STA_DEF 0x48490

1645

#define PCM_END_FSM_STA_DEF 0x08490

1646

#define PCM_END_FSM_STA_MASK 0x3fff0

1647

#define PCM_HANDSHAKE_SEND1 0xbeefbeef

1648

1649

#define PCM_WDT_TIMEOUT (30 * 32768)

1650

#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)

1651

1652

#define CON0_PCM_KICK (1U << 0)

1653

#define CON0_IM_KICK (1U << 1)

1654

#define CON0_IM_SLEEP_DVS (1U << 3)

1655

#define CON0_PCM_SW_RESET (1U << 15)

1656

#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16)

1657

1658

#define CON1_IM_SLAVE (1U << 0)

1659

#define CON1_MIF_APBEN (1U << 3)

1660

#define CON1_PCM_TIMER_EN (1U << 5)

1661

#define CON1_IM_NONRP_EN (1U << 6)

1662

#define CON1_PCM_WDT_EN (1U << 8)

1663

#define CON1_PCM_WDT_WAKE_MODE (1U << 9)

1664

#define CON1_SPM_SRAM_SLP_B (1U << 10)

1665

#define CON1_SPM_SRAM_ISO_B (1U << 11)

1666

#define CON1_EVENT_LOCK_EN (1U << 12)

1667

#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16)

1668

1669

#define PCM_PWRIO_EN_R0 (1U << 0)

1670

#define PCM_PWRIO_EN_R7 (1U << 7)

1671

#define PCM_RF_SYNC_R0 (1U << 16)

1672

#define PCM_RF_SYNC_R2 (1U << 18)

1673

#define PCM_RF_SYNC_R6 (1U << 22)

1674

#define PCM_RF_SYNC_R7 (1U << 23)

1675

1676

#define CC_SYSCLK0_EN_0 (1U << 0)

1677

#define CC_SYSCLK0_EN_1 (1U << 1)

1678

#define CC_SYSCLK1_EN_0 (1U << 2)

1679

#define CC_SYSCLK1_EN_1 (1U << 3)

1680

#define CC_SYSSETTLE_SEL (1U << 4)

1681

#define CC_LOCK_INFRA_DCM (1U << 5)

1682

#define CC_SRCLKENA_MASK_0 (1U << 6)

1683

#define CC_CXO32K_RM_EN_MD1 (1U << 9)

1684

#define CC_CXO32K_RM_EN_MD2 (1U << 10)

1685

#define CC_CLKSQ1_SEL (1U << 12)

1686

#define CC_DISABLE_DORM_PWR (1U << 14)

1687

#define CC_MD32_DCM_EN (1U << 18)

#define WFI_OP_AND 1

#define WFI_OP_OR 0

#define WAKE_MISC_PCM_TIMER (1U << 19)

1693

#define WAKE_MISC_CPU_WAKE (1U << 20)

1694

1695

/* define WAKE_SRC_XXX */

1696

#define WAKE_SRC_SPM_MERGE (1 << 0)

1697

#define WAKE_SRC_KP (1 << 2)

1698

#define WAKE_SRC_WDT (1 << 3)

1699

#define WAKE_SRC_GPT (1 << 4)

1700

#define WAKE_SRC_EINT (1 << 6)

1701

#define WAKE_SRC_LOW_BAT (1 << 9)

1702

#define WAKE_SRC_MD32 (1 << 10)

1703

#define WAKE_SRC_USB_CD (1 << 14)

1704

#define WAKE_SRC_USB_PDN (1 << 15)

1705

#define WAKE_SRC_AFE (1 << 20)

1706

#define WAKE_SRC_THERM (1 << 21)

1707

#define WAKE_SRC_SYSPWREQ (1 << 24)

1708

#define WAKE_SRC_SEJ (1 << 27)

1709

#define WAKE_SRC_ALL_MD32 (1 << 28)

1710

#define WAKE_SRC_CPU_IRQ (1 << 29)

1711

1712

#define spm_read(addr) mmio_read_32(addr)

1713

#define spm_write(addr, val) mmio_write_32(addr, val)

1714

1715

#endif /* SPM_H */