blob: 170d4cf815c8612174b9d2acca0b74052b177e33 [file] [log] [blame]
Yann Gautierbb836ee2018-07-16 17:55:07 +02001/*
Yann Gautierf3928f62019-02-14 11:15:03 +01002 * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
Yann Gautierbb836ee2018-07-16 17:55:07 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef STM32_I2C_H
8#define STM32_I2C_H
Yann Gautierbb836ee2018-07-16 17:55:07 +02009
10#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <lib/utils_def.h>
Yann Gautierbb836ee2018-07-16 17:55:07 +020013
14/* Bit definition for I2C_CR1 register */
15#define I2C_CR1_PE BIT(0)
16#define I2C_CR1_TXIE BIT(1)
17#define I2C_CR1_RXIE BIT(2)
18#define I2C_CR1_ADDRIE BIT(3)
19#define I2C_CR1_NACKIE BIT(4)
20#define I2C_CR1_STOPIE BIT(5)
21#define I2C_CR1_TCIE BIT(6)
22#define I2C_CR1_ERRIE BIT(7)
23#define I2C_CR1_DNF GENMASK(11, 8)
24#define I2C_CR1_ANFOFF BIT(12)
25#define I2C_CR1_SWRST BIT(13)
26#define I2C_CR1_TXDMAEN BIT(14)
27#define I2C_CR1_RXDMAEN BIT(15)
28#define I2C_CR1_SBC BIT(16)
29#define I2C_CR1_NOSTRETCH BIT(17)
30#define I2C_CR1_WUPEN BIT(18)
31#define I2C_CR1_GCEN BIT(19)
32#define I2C_CR1_SMBHEN BIT(22)
33#define I2C_CR1_SMBDEN BIT(21)
34#define I2C_CR1_ALERTEN BIT(22)
35#define I2C_CR1_PECEN BIT(23)
36
37/* Bit definition for I2C_CR2 register */
38#define I2C_CR2_SADD GENMASK(9, 0)
39#define I2C_CR2_RD_WRN BIT(10)
40#define I2C_CR2_RD_WRN_OFFSET 10U
41#define I2C_CR2_ADD10 BIT(11)
42#define I2C_CR2_HEAD10R BIT(12)
43#define I2C_CR2_START BIT(13)
44#define I2C_CR2_STOP BIT(14)
45#define I2C_CR2_NACK BIT(15)
46#define I2C_CR2_NBYTES GENMASK(23, 16)
47#define I2C_CR2_NBYTES_OFFSET 16U
48#define I2C_CR2_RELOAD BIT(24)
49#define I2C_CR2_AUTOEND BIT(25)
50#define I2C_CR2_PECBYTE BIT(26)
51
52/* Bit definition for I2C_OAR1 register */
53#define I2C_OAR1_OA1 GENMASK(9, 0)
54#define I2C_OAR1_OA1MODE BIT(10)
55#define I2C_OAR1_OA1EN BIT(15)
56
57/* Bit definition for I2C_OAR2 register */
58#define I2C_OAR2_OA2 GENMASK(7, 1)
59#define I2C_OAR2_OA2MSK GENMASK(10, 8)
60#define I2C_OAR2_OA2NOMASK 0
61#define I2C_OAR2_OA2MASK01 BIT(8)
62#define I2C_OAR2_OA2MASK02 BIT(9)
63#define I2C_OAR2_OA2MASK03 GENMASK(9, 8)
64#define I2C_OAR2_OA2MASK04 BIT(10)
65#define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10))
66#define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10))
67#define I2C_OAR2_OA2MASK07 GENMASK(10, 8)
68#define I2C_OAR2_OA2EN BIT(15)
69
70/* Bit definition for I2C_TIMINGR register */
71#define I2C_TIMINGR_SCLL GENMASK(7, 0)
72#define I2C_TIMINGR_SCLH GENMASK(15, 8)
73#define I2C_TIMINGR_SDADEL GENMASK(19, 16)
74#define I2C_TIMINGR_SCLDEL GENMASK(23, 20)
75#define I2C_TIMINGR_PRESC GENMASK(31, 28)
76
77/* Bit definition for I2C_TIMEOUTR register */
78#define I2C_TIMEOUTR_TIMEOUTA GENMASK(11, 0)
79#define I2C_TIMEOUTR_TIDLE BIT(12)
80#define I2C_TIMEOUTR_TIMOUTEN BIT(15)
81#define I2C_TIMEOUTR_TIMEOUTB GENMASK(27, 16)
82#define I2C_TIMEOUTR_TEXTEN BIT(31)
83
84/* Bit definition for I2C_ISR register */
85#define I2C_ISR_TXE BIT(0)
86#define I2C_ISR_TXIS BIT(1)
87#define I2C_ISR_RXNE BIT(2)
88#define I2C_ISR_ADDR BIT(3)
89#define I2C_ISR_NACKF BIT(4)
90#define I2C_ISR_STOPF BIT(5)
91#define I2C_ISR_TC BIT(6)
92#define I2C_ISR_TCR BIT(7)
93#define I2C_ISR_BERR BIT(8)
94#define I2C_ISR_ARLO BIT(9)
95#define I2C_ISR_OVR BIT(10)
96#define I2C_ISR_PECERR BIT(11)
97#define I2C_ISR_TIMEOUT BIT(12)
98#define I2C_ISR_ALERT BIT(13)
99#define I2C_ISR_BUSY BIT(15)
100#define I2C_ISR_DIR BIT(16)
101#define I2C_ISR_ADDCODE GENMASK(23, 17)
102
103/* Bit definition for I2C_ICR register */
104#define I2C_ICR_ADDRCF BIT(3)
105#define I2C_ICR_NACKCF BIT(4)
106#define I2C_ICR_STOPCF BIT(5)
107#define I2C_ICR_BERRCF BIT(8)
108#define I2C_ICR_ARLOCF BIT(9)
109#define I2C_ICR_OVRCF BIT(10)
110#define I2C_ICR_PECCF BIT(11)
111#define I2C_ICR_TIMOUTCF BIT(12)
112#define I2C_ICR_ALERTCF BIT(13)
113
Yann Gautierf3928f62019-02-14 11:15:03 +0100114enum i2c_speed_e {
115 I2C_SPEED_STANDARD, /* 100 kHz */
116 I2C_SPEED_FAST, /* 400 kHz */
117 I2C_SPEED_FAST_PLUS, /* 1 MHz */
118};
119
120#define STANDARD_RATE 100000
121#define FAST_RATE 400000
122#define FAST_PLUS_RATE 1000000
123
Yann Gautierbb836ee2018-07-16 17:55:07 +0200124struct stm32_i2c_init_s {
Yann Gautierf3928f62019-02-14 11:15:03 +0100125 uint32_t own_address1; /*
126 * Specifies the first device own
127 * address. This parameter can be a
128 * 7-bit or 10-bit address.
129 */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200130
Yann Gautierf3928f62019-02-14 11:15:03 +0100131 uint32_t addressing_mode; /*
132 * Specifies if 7-bit or 10-bit
133 * addressing mode is selected.
134 * This parameter can be a value of
135 * @ref I2C_ADDRESSING_MODE.
136 */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200137
Yann Gautierf3928f62019-02-14 11:15:03 +0100138 uint32_t dual_address_mode; /*
139 * Specifies if dual addressing mode is
140 * selected.
141 * This parameter can be a value of @ref
142 * I2C_DUAL_ADDRESSING_MODE.
143 */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200144
Yann Gautierf3928f62019-02-14 11:15:03 +0100145 uint32_t own_address2; /*
146 * Specifies the second device own
147 * address if dual addressing mode is
148 * selected. This parameter can be a
149 * 7-bit address.
150 */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200151
Yann Gautierf3928f62019-02-14 11:15:03 +0100152 uint32_t own_address2_masks; /*
153 * Specifies the acknowledge mask
154 * address second device own address
155 * if dual addressing mode is selected
156 * This parameter can be a value of @ref
157 * I2C_OWN_ADDRESS2_MASKS.
158 */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200159
Yann Gautierf3928f62019-02-14 11:15:03 +0100160 uint32_t general_call_mode; /*
161 * Specifies if general call mode is
162 * selected.
163 * This parameter can be a value of @ref
164 * I2C_GENERAL_CALL_ADDRESSING_MODE.
165 */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200166
Yann Gautierf3928f62019-02-14 11:15:03 +0100167 uint32_t no_stretch_mode; /*
168 * Specifies if nostretch mode is
169 * selected.
170 * This parameter can be a value of @ref
171 * I2C_NOSTRETCH_MODE.
172 */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200173
Yann Gautierf3928f62019-02-14 11:15:03 +0100174 uint32_t rise_time; /*
175 * Specifies the SCL clock pin rising
176 * time in nanoseconds.
177 */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200178
Yann Gautierf3928f62019-02-14 11:15:03 +0100179 uint32_t fall_time; /*
180 * Specifies the SCL clock pin falling
181 * time in nanoseconds.
182 */
183
184 enum i2c_speed_e speed_mode; /*
185 * Specifies the I2C clock source
186 * frequency mode.
187 * This parameter can be a value of @ref
188 * i2c_speed_mode_e.
189 */
190
191 int analog_filter; /*
192 * Specifies if the I2C analog noise
193 * filter is selected.
194 * This parameter can be 0 (filter
195 * off), all other values mean filter
196 * on.
197 */
198
199 uint8_t digital_filter_coef; /*
200 * Specifies the I2C digital noise
201 * filter coefficient.
202 * This parameter can be a value
203 * between 0 and
204 * STM32_I2C_DIGITAL_FILTER_MAX.
205 */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200206};
207
208enum i2c_state_e {
Yann Gautierf3928f62019-02-14 11:15:03 +0100209 I2C_STATE_RESET = 0x00U, /* Not yet initialized */
210 I2C_STATE_READY = 0x20U, /* Ready for use */
211 I2C_STATE_BUSY = 0x24U, /* Internal process ongoing */
212 I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission ongoing */
213 I2C_STATE_BUSY_RX = 0x22U, /* Data Reception ongoing */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200214};
215
216enum i2c_mode_e {
Yann Gautierf3928f62019-02-14 11:15:03 +0100217 I2C_MODE_NONE = 0x00U, /* No active communication */
218 I2C_MODE_MASTER = 0x10U, /* Communication in Master Mode */
219 I2C_MODE_SLAVE = 0x20U, /* Communication in Slave Mode */
220 I2C_MODE_MEM = 0x40U /* Communication in Memory Mode */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200221
222};
223
224#define I2C_ERROR_NONE 0x00000000U /* No error */
225#define I2C_ERROR_BERR 0x00000001U /* BERR error */
226#define I2C_ERROR_ARLO 0x00000002U /* ARLO error */
227#define I2C_ERROR_AF 0x00000004U /* ACKF error */
228#define I2C_ERROR_OVR 0x00000008U /* OVR error */
229#define I2C_ERROR_DMA 0x00000010U /* DMA transfer error */
230#define I2C_ERROR_TIMEOUT 0x00000020U /* Timeout error */
231#define I2C_ERROR_SIZE 0x00000040U /* Size Management error */
232
233struct i2c_handle_s {
234 uint32_t i2c_base_addr; /* Registers base address */
Yann Gautierf3928f62019-02-14 11:15:03 +0100235 unsigned int dt_status; /* DT nsec/sec status */
236 unsigned int clock; /* Clock reference */
237 uint8_t lock; /* Locking object */
238 enum i2c_state_e i2c_state; /* Communication state */
239 enum i2c_mode_e i2c_mode; /* Communication mode */
240 uint32_t i2c_err; /* Error code */
Yann Gautierbb836ee2018-07-16 17:55:07 +0200241};
242
243#define I2C_ADDRESSINGMODE_7BIT 0x00000001U
244#define I2C_ADDRESSINGMODE_10BIT 0x00000002U
245
246#define I2C_DUALADDRESS_DISABLE 0x00000000U
247#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
248
249#define I2C_GENERALCALL_DISABLE 0x00000000U
250#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
251
252#define I2C_NOSTRETCH_DISABLE 0x00000000U
253#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
254
255#define I2C_MEMADD_SIZE_8BIT 0x00000001U
256#define I2C_MEMADD_SIZE_16BIT 0x00000002U
257
Yann Gautierf3928f62019-02-14 11:15:03 +0100258#define I2C_RELOAD_MODE I2C_CR2_RELOAD
259#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
260#define I2C_SOFTEND_MODE 0x00000000U
Yann Gautierbb836ee2018-07-16 17:55:07 +0200261
Yann Gautierf3928f62019-02-14 11:15:03 +0100262#define I2C_NO_STARTSTOP 0x00000000U
263#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
264#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
Yann Gautierbb836ee2018-07-16 17:55:07 +0200265 I2C_CR2_RD_WRN)
Yann Gautierf3928f62019-02-14 11:15:03 +0100266#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
Yann Gautierbb836ee2018-07-16 17:55:07 +0200267
268#define I2C_FLAG_TXE I2C_ISR_TXE
269#define I2C_FLAG_TXIS I2C_ISR_TXIS
270#define I2C_FLAG_RXNE I2C_ISR_RXNE
271#define I2C_FLAG_ADDR I2C_ISR_ADDR
272#define I2C_FLAG_AF I2C_ISR_NACKF
273#define I2C_FLAG_STOPF I2C_ISR_STOPF
274#define I2C_FLAG_TC I2C_ISR_TC
275#define I2C_FLAG_TCR I2C_ISR_TCR
276#define I2C_FLAG_BERR I2C_ISR_BERR
277#define I2C_FLAG_ARLO I2C_ISR_ARLO
278#define I2C_FLAG_OVR I2C_ISR_OVR
279#define I2C_FLAG_PECERR I2C_ISR_PECERR
280#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
281#define I2C_FLAG_ALERT I2C_ISR_ALERT
282#define I2C_FLAG_BUSY I2C_ISR_BUSY
283#define I2C_FLAG_DIR I2C_ISR_DIR
284
285#define I2C_RESET_CR2 (I2C_CR2_SADD | I2C_CR2_HEAD10R | \
286 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
287 I2C_CR2_RD_WRN)
288
Yann Gautierf3928f62019-02-14 11:15:03 +0100289#define I2C_TIMEOUT_BUSY_MS 25U
290
291#define I2C_ANALOGFILTER_ENABLE 0x00000000U
Yann Gautierbb836ee2018-07-16 17:55:07 +0200292#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
293
Yann Gautierf3928f62019-02-14 11:15:03 +0100294/* STM32 specific defines */
295#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
296#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
297#define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD
298#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
299#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
300#define STM32_I2C_DIGITAL_FILTER_MAX 16
Yann Gautierbb836ee2018-07-16 17:55:07 +0200301
Yann Gautierf3928f62019-02-14 11:15:03 +0100302int stm32_i2c_get_setup_from_fdt(void *fdt, int node,
303 struct stm32_i2c_init_s *init);
304int stm32_i2c_init(struct i2c_handle_s *hi2c,
305 struct stm32_i2c_init_s *init_data);
Yann Gautierbb836ee2018-07-16 17:55:07 +0200306int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
307 uint16_t mem_addr, uint16_t mem_add_size,
Yann Gautierf3928f62019-02-14 11:15:03 +0100308 uint8_t *p_data, uint16_t size, uint32_t timeout_ms);
Yann Gautierbb836ee2018-07-16 17:55:07 +0200309int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
310 uint16_t mem_addr, uint16_t mem_add_size,
Yann Gautierf3928f62019-02-14 11:15:03 +0100311 uint8_t *p_data, uint16_t size, uint32_t timeout_ms);
312int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint16_t dev_addr,
313 uint8_t *p_data, uint16_t size,
314 uint32_t timeout_ms);
315int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint16_t dev_addr,
316 uint8_t *p_data, uint16_t size,
317 uint32_t timeout_ms);
318bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr,
319 uint32_t trials, uint32_t timeout_ms);
Yann Gautierbb836ee2018-07-16 17:55:07 +0200320
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000321#endif /* STM32_I2C_H */