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git01.mediatek.com / filogic / atf / 08c69d10acf292c9b5fbc34e50429fe028c82cd0 / . / plat / xilinx / zynqmp / platform.mk
blob: f806d4605938bc4d72e6fe5d628d854076017754 [file] [log] [blame]
Antonio Nino Diaz493bf332016-12-14 14:31:32 +0000[diff] [blame]1#
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]3#
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4# SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]5
Soren Brinkmannba8309d2017-04-06 11:44:27 -0700[diff] [blame]6override ERRATA_A53_855873 := 1
Masahiro Yamada8cf895c2016-12-19 17:41:47 +0900[diff] [blame]7override ENABLE_PLAT_COMPAT := 0
8override PROGRAMMABLE_RESET_ADDRESS := 1
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]9PSCI_EXTENDED_STATE_ID := 1
10A53_DISABLE_NON_TEMPORAL_HINT := 0
Soren Brinkmann6d1ba582016-07-08 14:45:14 -0700[diff] [blame]11SEPARATE_CODE_AND_RODATA := 1
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530[diff] [blame]12ZYNQMP_WDT_RESTART := 0
Masahiro Yamada8cf895c2016-12-19 17:41:47 +0900[diff] [blame]13override RESET_TO_BL31 := 1
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]14
David Cunadoc5b0c0f2017-10-31 23:19:21 +0000[diff] [blame]15# Do not enable SVE
16ENABLE_SVE_FOR_NS := 0
17
Dimitris Papastamos8e5bd5e2018-01-24 16:41:14 +0000[diff] [blame]18WORKAROUND_CVE_2017_5715 := 0
19
Siva Durga Prasad Paladugu9cfc47c2018-08-13 16:40:04 +0530[diff] [blame]20ARM_XLAT_TABLES_LIB_V1 := 1
21$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
22$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
23
Soren Brinkmann4a9ca042016-04-14 10:27:00 -0700[diff] [blame]24ifdef ZYNQMP_ATF_MEM_BASE
25 $(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
26
27 ifndef ZYNQMP_ATF_MEM_SIZE
28 $(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE")
29 endif
30 $(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE))
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]31
Soren Brinkmann4a9ca042016-04-14 10:27:00 -0700[diff] [blame]32 ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
33 $(eval $(call add_define,ZYNQMP_ATF_MEM_PROGBITS_SIZE))
34 endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]35endif
36
Soren Brinkmann4a9ca042016-04-14 10:27:00 -0700[diff] [blame]37ifdef ZYNQMP_BL32_MEM_BASE
38 $(eval $(call add_define,ZYNQMP_BL32_MEM_BASE))
39
40 ifndef ZYNQMP_BL32_MEM_SIZE
41 $(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE")
42 endif
43 $(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
44endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]45
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -0700[diff] [blame]46ZYNQMP_CONSOLE ?= cadence
47$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
48
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530[diff] [blame]49ifdef ZYNQMP_WDT_RESTART
50$(eval $(call add_define,ZYNQMP_WDT_RESTART))
51endif
52
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]53PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
54 -Iinclude/plat/arm/common/aarch64/ \
55 -Iplat/xilinx/zynqmp/include/ \
Wendy Liangf8fec362017-09-06 09:39:55 -0700[diff] [blame]56 -Iplat/xilinx/zynqmp/pm_service/ \
57 -Iplat/xilinx/zynqmp/ipi_mailbox_service/
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]58
Soby Mathewcc037c12016-04-08 16:42:58 +0100[diff] [blame]59PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
60 lib/xlat_tables/aarch64/xlat_tables.c \
Soren Brinkmanne5bdcaa2016-06-22 09:02:56 -0700[diff] [blame]61 drivers/delay_timer/delay_timer.c \
62 drivers/delay_timer/generic_delay_timer.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]63 drivers/arm/gic/common/gic_common.c \
64 drivers/arm/gic/v2/gicv2_main.c \
65 drivers/arm/gic/v2/gicv2_helpers.c \
Soby Mathew17231132016-08-08 12:33:06 +0100[diff] [blame]66 drivers/cadence/uart/aarch64/cdns_console.S \
67 drivers/console/aarch64/console.S \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]68 plat/arm/common/aarch64/arm_helpers.S \
69 plat/arm/common/arm_cci.c \
Soby Mathew0eb965b2016-07-07 08:45:56 +0100[diff] [blame]70 plat/arm/common/arm_common.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]71 plat/arm/common/arm_gicv2.c \
72 plat/common/plat_gicv2.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]73 plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \
74 plat/xilinx/zynqmp/aarch64/zynqmp_common.c
75
76BL31_SOURCES += drivers/arm/cci/cci.c \
77 lib/cpus/aarch64/aem_generic.S \
78 lib/cpus/aarch64/cortex_a53.S \
Soby Mathewf6c41082016-05-03 12:31:18 +0100[diff] [blame]79 plat/common/plat_psci_common.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]80 plat/xilinx/zynqmp/bl31_zynqmp_setup.c \
81 plat/xilinx/zynqmp/plat_psci.c \
82 plat/xilinx/zynqmp/plat_zynqmp.c \
Michal Simekef8f5592015-06-15 14:22:50 +0200[diff] [blame]83 plat/xilinx/zynqmp/plat_startup.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]84 plat/xilinx/zynqmp/plat_topology.c \
85 plat/xilinx/zynqmp/sip_svc_setup.c \
Wendy Liang3aebacf2017-09-13 11:02:42 -0700[diff] [blame]86 plat/xilinx/zynqmp/zynqmp_ipi.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]87 plat/xilinx/zynqmp/pm_service/pm_svc_main.c \
88 plat/xilinx/zynqmp/pm_service/pm_api_sys.c \
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]89 plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c \
Rajan Vaja5529a012018-01-17 02:39:23 -0800[diff] [blame]90 plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c \
Rajan Vaja35116132018-01-17 02:39:25 -0800[diff] [blame]91 plat/xilinx/zynqmp/pm_service/pm_api_clock.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]92 plat/xilinx/zynqmp/pm_service/pm_ipi.c \
Wendy Liangf8fec362017-09-06 09:39:55 -0700[diff] [blame]93 plat/xilinx/zynqmp/pm_service/pm_client.c \
94 plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c