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git01.mediatek.com / filogic / atf / 08834ce17fa3c8439573d9bdcec45fdb5d261d15 / . / plat / renesas / rcar / bl2_secure_setting.c
blob: c0d49debc711b601ea6de5a239d268a03f2bc7aa [file] [log] [blame]
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame]1/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include "axi_registers.h"
8#include "lifec_registers.h"
9#include "micro_delay.h"
10#include "mmio.h"
11#include "utils_def.h"
12
13static void lifec_security_setting(void);
14static void axi_security_setting(void);
15
16static const struct {
17 uint32_t reg;
18 uint32_t val;
19} lifec[] = {
20 /** LIFEC0 (SECURITY) settings */
21 /* Security attribute setting for master ports */
22 /* Bit 0: ARM realtime core (Cortex-R7) master port */
23 /* 0: Non-Secure */
24 {
25 SEC_SRC, 0x0000001EU},
26 /** Security attribute setting for slave ports 0 to 15 */
27 /* {SEC_SEL0, 0xFFFFFFFFU}, */
28 /* {SEC_SEL1, 0xFFFFFFFFU}, */
29 /* {SEC_SEL2, 0xFFFFFFFFU}, */
30 /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports */
31 /* 0: registers accessed from secure resource only */
32 /* Bit 9: DBSC4 register access slave ports. */
33 /* 0: registers accessed from secure resource only. */
34#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
35 {
36 SEC_SEL3, 0xFFF7FDFFU},
37#else
38 {
39 SEC_SEL3, 0xFFFFFFFFU},
40#endif
41 /* {SEC_SEL4, 0xFFFFFFFFU}, */
42 /* Bit 6: Boot ROM slave ports. */
43 /* 0: registers accessed from secure resource only */
44 {
45 SEC_SEL5, 0xFFFFFFBFU},
46 /* Bit13: SCEG PKA (secure APB) slave ports */
47 /* 0: registers accessed from secure resource only */
48 /* 1: Reserved[R-Car E3] */
49 /* Bit12: SCEG PKA (public APB) slave ports */
50 /* 0: registers accessed from secure resource only */
51 /* 1: Reserved[R-Car E3] */
52 /* Bit10: SCEG Secure Core slave ports */
53 /* 0: registers accessed from secure resource only */
54#if RCAR_LSI == RCAR_E3
55 {
56 SEC_SEL6, 0xFFFFFBFFU},
57#else
58 {
59 SEC_SEL6, 0xFFFFCBFFU},
60#endif
61 /* {SEC_SEL7, 0xFFFFFFFFU}, */
62 /* {SEC_SEL8, 0xFFFFFFFFU}, */
63 /* {SEC_SEL9, 0xFFFFFFFFU}, */
64 /* {SEC_SEL10, 0xFFFFFFFFU}, */
65 /* {SEC_SEL11, 0xFFFFFFFFU}, */
66 /* {SEC_SEL12, 0xFFFFFFFFU}, */
67 /* Bit22: RPC slave ports. */
68 /* 0: registers accessed from secure resource only. */
Jorge Ramirez-Ortiz87c04052018-11-19 19:26:56 +0100[diff] [blame]69#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
70 {SEC_SEL13, 0xFFBFFFFFU},
71#endif
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame]72 /* Bit27: System Timer (SCMT) slave ports */
73 /* 0: registers accessed from secure resource only */
74 /* Bit26: System Watchdog Timer (SWDT) slave ports */
75 /* 0: registers accessed from secure resource only */
76 {
77 SEC_SEL14, 0xF3FFFFFFU},
78 /* Bit13: RST slave ports. */
79 /* 0: registers accessed from secure resource only */
80 /* Bit 7: Life Cycle 0 slave ports */
81 /* 0: registers accessed from secure resource only */
82 {
83 SEC_SEL15, 0xFFFFFF3FU},
84 /** Security group 0 attribute setting for master ports 0 */
85 /** Security group 1 attribute setting for master ports 0 */
86 /* {SEC_GRP0CR0, 0x00000000U}, */
87 /* {SEC_GRP1CR0, 0x00000000U}, */
88 /** Security group 0 attribute setting for master ports 1 */
89 /** Security group 1 attribute setting for master ports 1 */
90 /* {SEC_GRP0CR1, 0x00000000U}, */
91 /* {SEC_GRP1CR1, 0x00000000U}, */
92 /** Security group 0 attribute setting for master ports 2 */
93 /** Security group 1 attribute setting for master ports 2 */
94 /* Bit17: SCEG Secure Core master ports. */
95 /* SecurityGroup3 */
96 {
97 SEC_GRP0CR2, 0x00020000U}, {
98 SEC_GRP1CR2, 0x00020000U},
99 /** Security group 0 attribute setting for master ports 3 */
100 /** Security group 1 attribute setting for master ports 3 */
101 /* {SEC_GRP0CR3, 0x00000000U}, */
102 /* {SEC_GRP1CR3, 0x00000000U}, */
103 /** Security group 0 attribute setting for slave ports 0 */
104 /** Security group 1 attribute setting for slave ports 0 */
105 /* {SEC_GRP0COND0, 0x00000000U}, */
106 /* {SEC_GRP1COND0, 0x00000000U}, */
107 /** Security group 0 attribute setting for slave ports 1 */
108 /** Security group 1 attribute setting for slave ports 1 */
109 /* {SEC_GRP0COND1, 0x00000000U}, */
110 /* {SEC_GRP1COND1, 0x00000000U}, */
111 /** Security group 0 attribute setting for slave ports 2 */
112 /** Security group 1 attribute setting for slave ports 2 */
113 /* {SEC_GRP0COND2, 0x00000000U}, */
114 /* {SEC_GRP1COND2, 0x00000000U}, */
115 /** Security group 0 attribute setting for slave ports 3 */
116 /** Security group 1 attribute setting for slave ports 3 */
117 /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports. */
118 /* SecurityGroup3 */
119 /* Bit 9: DBSC4 register access slave ports. */
120 /* SecurityGroup3 */
121#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
122 {
123 SEC_GRP0COND3, 0x00080200U}, {
124 SEC_GRP1COND3, 0x00080200U},
125#else
126 {
127 SEC_GRP0COND3, 0x00000000U}, {
128 SEC_GRP1COND3, 0x00000000U},
129#endif
130 /** Security group 0 attribute setting for slave ports 4 */
131 /** Security group 1 attribute setting for slave ports 4 */
132 /* {SEC_GRP0COND4, 0x00000000U}, */
133 /* {SEC_GRP1COND4, 0x00000000U}, */
134 /** Security group 0 attribute setting for slave ports 5 */
135 /** Security group 1 attribute setting for slave ports 5 */
136 /* Bit 6: Boot ROM slave ports */
137 /* SecurityGroup3 */
138 {
139 SEC_GRP0COND5, 0x00000040U}, {
140 SEC_GRP1COND5, 0x00000040U},
141 /** Security group 0 attribute setting for slave ports 6 */
142 /** Security group 1 attribute setting for slave ports 6 */
143 /* Bit13: SCEG PKA (secure APB) slave ports */
144 /* SecurityGroup3 */
145 /* Reserved[R-Car E3] */
146 /* Bit12: SCEG PKA (public APB) slave ports */
147 /* SecurityGroup3 */
148 /* Reserved[R-Car E3] */
149 /* Bit10: SCEG Secure Core slave ports */
150 /* SecurityGroup3 */
151#if RCAR_LSI == RCAR_E3
152 {
153 SEC_GRP0COND6, 0x00000400U}, {
154 SEC_GRP1COND6, 0x00000400U},
155#else
156 {
157 SEC_GRP0COND6, 0x00003400U}, {
158 SEC_GRP1COND6, 0x00003400U},
159#endif
160 /** Security group 0 attribute setting for slave ports 7 */
161 /** Security group 1 attribute setting for slave ports 7 */
162 /* {SEC_GRP0COND7, 0x00000000U}, */
163 /* {SEC_GRP1COND7, 0x00000000U}, */
164 /** Security group 0 attribute setting for slave ports 8 */
165 /** Security group 1 attribute setting for slave ports 8 */
166 /* {SEC_GRP0COND8, 0x00000000U}, */
167 /* {SEC_GRP1COND8, 0x00000000U}, */
168 /** Security group 0 attribute setting for slave ports 9 */
169 /** Security group 1 attribute setting for slave ports 9 */
170 /* {SEC_GRP0COND9, 0x00000000U}, */
171 /* {SEC_GRP1COND9, 0x00000000U}, */
172 /** Security group 0 attribute setting for slave ports 10 */
173 /** Security group 1 attribute setting for slave ports 10 */
174 /* {SEC_GRP0COND10, 0x00000000U}, */
175 /* {SEC_GRP1COND10, 0x00000000U}, */
176 /** Security group 0 attribute setting for slave ports 11 */
177 /** Security group 1 attribute setting for slave ports 11 */
178 /* {SEC_GRP0COND11, 0x00000000U}, */
179 /* {SEC_GRP1COND11, 0x00000000U}, */
180 /** Security group 0 attribute setting for slave ports 12 */
181 /** Security group 1 attribute setting for slave ports 12 */
182 /* {SEC_GRP0COND12, 0x00000000U}, */
183 /* {SEC_GRP1COND12, 0x00000000U}, */
184 /** Security group 0 attribute setting for slave ports 13 */
185 /** Security group 1 attribute setting for slave ports 13 */
186 /* Bit22: RPC slave ports. */
187 /* SecurityGroup3 */
Jorge Ramirez-Ortiz87c04052018-11-19 19:26:56 +0100[diff] [blame]188#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
189 {SEC_GRP0COND13, 0x00400000U},
190 {SEC_GRP1COND13, 0x00400000U},
191#endif
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame]192 /** Security group 0 attribute setting for slave ports 14 */
193 /** Security group 1 attribute setting for slave ports 14 */
194 /* Bit26: System Timer (SCMT) slave ports */
195 /* SecurityGroup3 */
196 /* Bit27: System Watchdog Timer (SWDT) slave ports */
197 /* SecurityGroup3 */
198 {
199 SEC_GRP0COND14, 0x0C000000U}, {
200 SEC_GRP1COND14, 0x0C000000U},
201 /** Security group 0 attribute setting for slave ports 15 */
202 /** Security group 1 attribute setting for slave ports 15 */
203 /* Bit13: RST slave ports */
204 /* SecurityGroup3 */
205 /* Bit 7: Life Cycle 0 slave ports */
206 /* SecurityGroup3 */
207 /* Bit 6: TDBG slave ports */
208 /* SecurityGroup3 */
209 {
210 SEC_GRP0COND15, 0x000000C0U}, {
211 SEC_GRP1COND15, 0x000000C0U},
212 /** Security write protection attribute setting slave ports 0 */
213 /* {SEC_READONLY0, 0x00000000U}, */
214 /** Security write protection attribute setting slave ports 1 */
215 /* {SEC_READONLY1, 0x00000000U}, */
216 /** Security write protection attribute setting slave ports 2 */
217 /* {SEC_READONLY2, 0x00000000U}, */
218 /** Security write protection attribute setting slave ports 3 */
219 /* {SEC_READONLY3, 0x00000000U}, */
220 /** Security write protection attribute setting slave ports 4 */
221 /* {SEC_READONLY4, 0x00000000U}, */
222 /** Security write protection attribute setting slave ports 5 */
223 /* {SEC_READONLY5, 0x00000000U}, */
224 /** Security write protection attribute setting slave ports 6 */
225 /* {SEC_READONLY6, 0x00000000U}, */
226 /** Security write protection attribute setting slave ports 7 */
227 /* {SEC_READONLY7, 0x00000000U}, */
228 /** Security write protection attribute setting slave ports 8 */
229 /* {SEC_READONLY8, 0x00000000U}, */
230 /** Security write protection attribute setting slave ports 9 */
231 /* {SEC_READONLY9, 0x00000000U}, */
232 /** Security write protection attribute setting slave ports 10 */
233 /* {SEC_READONLY10, 0x00000000U}, */
234 /** Security write protection attribute setting slave ports 11 */
235 /* {SEC_READONLY11, 0x00000000U}, */
236 /** Security write protection attribute setting slave ports 12 */
237 /* {SEC_READONLY12, 0x00000000U}, */
238 /** Security write protection attribute setting slave ports 13 */
239 /* {SEC_READONLY13, 0x00000000U}, */
240 /** Security write protection attribute setting slave ports 14 */
241 /* {SEC_READONLY14, 0x00000000U}, */
242 /** Security write protection attribute setting slave ports 15 */
243 /* {SEC_READONLY15, 0x00000000U} */
244};
245
246/* AXI settings */
247static const struct {
248 uint32_t reg;
249 uint32_t val;
250} axi[] = {
251 /* DRAM protection */
252 /* AXI dram protected area division */
253 {
254 AXI_DPTDIVCR0, 0x0E0403F0U}, {
255 AXI_DPTDIVCR1, 0x0E0407E0U}, {
256 AXI_DPTDIVCR2, 0x0E080000U}, {
257 AXI_DPTDIVCR3, 0x0E080000U}, {
258 AXI_DPTDIVCR4, 0x0E080000U}, {
259 AXI_DPTDIVCR5, 0x0E080000U}, {
260 AXI_DPTDIVCR6, 0x0E080000U}, {
261 AXI_DPTDIVCR7, 0x0E080000U}, {
262 AXI_DPTDIVCR8, 0x0E080000U}, {
263 AXI_DPTDIVCR9, 0x0E080000U}, {
264 AXI_DPTDIVCR10, 0x0E080000U}, {
265 AXI_DPTDIVCR11, 0x0E080000U}, {
266 AXI_DPTDIVCR12, 0x0E080000U}, {
267 AXI_DPTDIVCR13, 0x0E080000U}, {
268 AXI_DPTDIVCR14, 0x0E080000U},
269 /* AXI dram protected area setting */
270 {
271 AXI_DPTCR0, 0x0E000000U}, {
272 AXI_DPTCR1, 0x0E000E0EU}, {
273 AXI_DPTCR2, 0x0E000000U}, {
274 AXI_DPTCR3, 0x0E000000U}, {
275 AXI_DPTCR4, 0x0E000000U}, {
276 AXI_DPTCR5, 0x0E000000U}, {
277 AXI_DPTCR6, 0x0E000000U}, {
278 AXI_DPTCR7, 0x0E000000U}, {
279 AXI_DPTCR8, 0x0E000000U}, {
280 AXI_DPTCR9, 0x0E000000U}, {
281 AXI_DPTCR10, 0x0E000000U}, {
282 AXI_DPTCR11, 0x0E000000U}, {
283 AXI_DPTCR12, 0x0E000000U}, {
284 AXI_DPTCR13, 0x0E000000U}, {
285 AXI_DPTCR14, 0x0E000000U}, {
286 AXI_DPTCR15, 0x0E000000U},
287 /* SRAM ptotection */
288 /* AXI sram protected area division */
289 {
290 AXI_SPTDIVCR0, 0x0E0E6304U}, {
291 AXI_SPTDIVCR1, 0x0E0E6360U}, {
292 AXI_SPTDIVCR2, 0x0E0E6360U}, {
293 AXI_SPTDIVCR3, 0x0E0E6360U}, {
294 AXI_SPTDIVCR4, 0x0E0E6360U}, {
295 AXI_SPTDIVCR5, 0x0E0E6360U}, {
296 AXI_SPTDIVCR6, 0x0E0E6360U}, {
297 AXI_SPTDIVCR7, 0x0E0E6360U}, {
298 AXI_SPTDIVCR8, 0x0E0E6360U}, {
299 AXI_SPTDIVCR9, 0x0E0E6360U}, {
300 AXI_SPTDIVCR10, 0x0E0E6360U}, {
301 AXI_SPTDIVCR11, 0x0E0E6360U}, {
302 AXI_SPTDIVCR12, 0x0E0E6360U}, {
303 AXI_SPTDIVCR13, 0x0E0E6360U}, {
304 AXI_SPTDIVCR14, 0x0E0E6360U},
305 /* AXI sram protected area setting */
306 {
307 AXI_SPTCR0, 0x0E000E0EU}, {
308 AXI_SPTCR1, 0x0E000000U}, {
309 AXI_SPTCR2, 0x0E000000U}, {
310 AXI_SPTCR3, 0x0E000000U}, {
311 AXI_SPTCR4, 0x0E000000U}, {
312 AXI_SPTCR5, 0x0E000000U}, {
313 AXI_SPTCR6, 0x0E000000U}, {
314 AXI_SPTCR7, 0x0E000000U}, {
315 AXI_SPTCR8, 0x0E000000U}, {
316 AXI_SPTCR9, 0x0E000000U}, {
317 AXI_SPTCR10, 0x0E000000U}, {
318 AXI_SPTCR11, 0x0E000000U}, {
319 AXI_SPTCR12, 0x0E000000U}, {
320 AXI_SPTCR13, 0x0E000000U}, {
321 AXI_SPTCR14, 0x0E000000U}, {
322 AXI_SPTCR15, 0x0E000000U}
323};
324
325static void lifec_security_setting(void)
326{
327 uint32_t i;
328
329 for (i = 0; i < ARRAY_SIZE(lifec); i++)
330 mmio_write_32(lifec[i].reg, lifec[i].val);
331}
332
333/* SRAM/DRAM protection setting */
334static void axi_security_setting(void)
335{
336 uint32_t i;
337
338 for (i = 0; i < ARRAY_SIZE(axi); i++)
339 mmio_write_32(axi[i].reg, axi[i].val);
340}
341
342void bl2_secure_setting(void)
343{
344 const uint32_t delay = 10;
345
346 lifec_security_setting();
347 axi_security_setting();
348 rcar_micro_delay(delay);
349
350 return;
351}