blob: 0fa064b7a47ccc59c53777b69013675aa79d19ca [file] [log] [blame]
Yann Gautierf7907022021-09-08 17:14:21 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/clock/stm32mp13-clksrc.h>
10#include "stm32mp135.dtsi"
11#include "stm32mp13xf.dtsi"
12#include "stm32mp13-ddr3-1x4Gb-1066-binF.dtsi"
13#include "stm32mp13-pinctrl.dtsi"
14
15/ {
16 model = "STMicroelectronics STM32MP135F-DK Discovery Board";
17 compatible = "st,stm32mp135f-dk", "st,stm32mp135";
18
19 aliases {
20 serial0 = &uart4;
21 serial1 = &usart1;
22 serial2 = &uart8;
23 serial3 = &usart2;
24 };
25
26 chosen {
27 stdout-path = "serial0:115200n8";
28 };
29
30 memory@c0000000 {
31 device_type = "memory";
32 reg = <0xc0000000 0x20000000>;
33 };
34
35 vin: vin {
36 compatible = "regulator-fixed";
37 regulator-name = "vin";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 regulator-always-on;
41 };
42
43 v3v3_ao: v3v3_ao {
44 compatible = "regulator-fixed";
45 regulator-name = "v3v3_ao";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 regulator-always-on;
49 };
50};
51
52&bsec {
53 board_id: board_id@f0 {
54 reg = <0xf0 0x4>;
55 st,non-secure-otp;
56 };
57};
58
59&cpu0 {
60 cpu-supply = <&vddcpu>;
61};
62
63&hash {
64 status = "okay";
65};
66
67&i2c4 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&i2c4_pins_a>;
70 i2c-scl-rising-time-ns = <185>;
71 i2c-scl-falling-time-ns = <20>;
72 clock-frequency = <400000>;
73 status = "disabled";
74 secure-status = "okay";
75
76 pmic: stpmic@33 {
77 compatible = "st,stpmic1";
78 reg = <0x33>;
79
80 status = "disabled";
81 secure-status = "okay";
82
83 regulators {
84 compatible = "st,stpmic1-regulators";
85 buck1-supply = <&vin>;
86 buck2-supply = <&vin>;
87 buck3-supply = <&vin>;
88 buck4-supply = <&vin>;
89 ldo1-supply = <&vin>;
90 ldo4-supply = <&vin>;
91 ldo5-supply = <&vin>;
92 ldo6-supply = <&vin>;
93 vref_ddr-supply = <&vin>;
94 pwr_sw1-supply = <&bst_out>;
95 pwr_sw2-supply = <&v3v3_ao>;
96
97 vddcpu: buck1 {
98 regulator-name = "vddcpu";
99 regulator-min-microvolt = <1250000>;
100 regulator-max-microvolt = <1250000>;
101 regulator-always-on;
102 regulator-over-current-protection;
103 };
104
105 vdd_ddr: buck2 {
106 regulator-name = "vdd_ddr";
107 regulator-min-microvolt = <1350000>;
108 regulator-max-microvolt = <1350000>;
109 regulator-always-on;
110 regulator-over-current-protection;
111 };
112
113 vdd: buck3 {
114 regulator-name = "vdd";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 regulator-always-on;
118 st,mask-reset;
119 regulator-over-current-protection;
120 };
121
122 vddcore: buck4 {
123 regulator-name = "vddcore";
124 regulator-min-microvolt = <1250000>;
125 regulator-max-microvolt = <1250000>;
126 regulator-always-on;
127 regulator-over-current-protection;
128 };
129
130 vdd_adc: ldo1 {
131 regulator-name = "vdd_adc";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 };
135
136 vdd_usb: ldo4 {
137 regulator-name = "vdd_usb";
138 regulator-min-microvolt = <3300000>;
139 regulator-max-microvolt = <3300000>;
140 };
141
142 vdd_sd: ldo5 {
143 regulator-name = "vdd_sd";
144 regulator-min-microvolt = <3300000>;
145 regulator-max-microvolt = <3300000>;
146 regulator-boot-on;
147 };
148
149 v1v8_periph: ldo6 {
150 regulator-name = "v1v8_periph";
151 regulator-min-microvolt = <1800000>;
152 regulator-max-microvolt = <1800000>;
153 };
154
155 vref_ddr: vref_ddr {
156 regulator-name = "vref_ddr";
157 regulator-always-on;
158 };
159
160 bst_out: boost {
161 regulator-name = "bst_out";
162 };
163
164 v3v3_sw: pwr_sw2 {
165 regulator-name = "v3v3_sw";
166 regulator-active-discharge = <1>;
167 regulator-always-on;
168 };
169 };
170 };
171};
172
173&iwdg2 {
174 timeout-sec = <32>;
175 status = "okay";
176};
177
178&nvmem_layout {
179 nvmem-cells = <&cfg0_otp>,
180 <&part_number_otp>,
181 <&monotonic_otp>,
182 <&nand_otp>,
183 <&nand2_otp>,
184 <&uid_otp>,
185 <&hw2_otp>,
186 <&pkh_otp>,
187 <&board_id>;
188
189 nvmem-cell-names = "cfg0_otp",
190 "part_number_otp",
191 "monotonic_otp",
192 "nand_otp",
193 "nand2_otp",
194 "uid_otp",
195 "hw2_otp",
196 "pkh_otp",
197 "board_id";
198};
199
200&pka {
201 secure-status = "okay";
202};
203
204&pwr_regulators {
205 vdd-supply = <&vdd>;
206 vdd_3v3_usbfs-supply = <&vdd_usb>;
207};
208
209&rcc {
210 st,clksrc = <
211 CLK_MPU_PLL1P
212 CLK_AXI_PLL2P
213 CLK_MLAHBS_PLL3
214 CLK_CKPER_HSE
215 CLK_RTC_LSE
216 CLK_SDMMC1_PLL4P
217 CLK_SDMMC2_PLL4P
218 CLK_STGEN_HSE
219 CLK_USBPHY_HSE
220 CLK_I2C4_HSI
221 CLK_USBO_USBPHY
222 CLK_I2C12_HSI
223 CLK_UART2_HSI
224 CLK_UART4_HSI
225 CLK_SAES_AXI
226 >;
227
228 st,clkdiv = <
229 DIV(DIV_AXI, 0)
230 DIV(DIV_MLAHB, 0)
231 DIV(DIV_APB1, 1)
232 DIV(DIV_APB2, 1)
233 DIV(DIV_APB3, 1)
234 DIV(DIV_APB4, 1)
235 DIV(DIV_APB5, 2)
236 DIV(DIV_APB6, 1)
237 DIV(DIV_RTC, 0)
238 >;
239
240 st,pll_vco {
241 pll1_vco_1300Mhz: pll1-vco-1300Mhz {
242 src = < CLK_PLL12_HSE >;
243 divmn = < 2 80 >;
244 frac = < 0x800 >;
245 };
246
247 pll2_vco_1066Mhz: pll2-vco-1066Mhz {
248 src = < CLK_PLL12_HSE >;
249 divmn = < 2 65 >;
250 frac = < 0x1400 >;
251 };
252
253 pll3_vco_417_8Mhz: pll2-vco-417_8Mhz {
254 src = < CLK_PLL3_HSE >;
255 divmn = < 1 33 >;
256 frac = < 0x1a04 >;
257 };
258
259 pll4_vco_600Mhz: pll2-vco-600Mhz {
260 src = < CLK_PLL4_HSE >;
261 divmn = < 1 49 >;
262 };
263 };
264
265 /* VCO = 1300.0 MHz => P = 650 (CPU) */
266 pll1:st,pll@0 {
267 compatible = "st,stm32mp1-pll";
268 reg = <0>;
269
270 st,pll = < &pll1_cfg1 >;
271
272 pll1_cfg1: pll1_cfg1 {
273 st,pll_vco = < &pll1_vco_1300Mhz >;
274 st,pll_div_pqr = < 0 1 1 >;
275 };
276 };
277
278 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
279 pll2:st,pll@1 {
280 compatible = "st,stm32mp1-pll";
281 reg = <1>;
282
283 st,pll = < &pll2_cfg1 >;
284
285 pll2_cfg1: pll2_cfg1 {
286 st,pll_vco = < &pll2_vco_1066Mhz >;
287 st,pll_div_pqr = < 1 1 0 >;
288 };
289 };
290
291 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 209 */
292 pll3:st,pll@2 {
293 compatible = "st,stm32mp1-pll";
294 reg = <2>;
295
296 st,pll = < &pll3_cfg1 >;
297
298 pll3_cfg1: pll3_cfg1 {
299 st,pll_vco = < &pll3_vco_417_8Mhz >;
300 st,pll_div_pqr = < 1 16 1 >;
301 };
302 };
303
304 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 100 */
305 pll4:st,pll@3 {
306 compatible = "st,stm32mp1-pll";
307 reg = <3>;
308
309 st,pll = < &pll4_cfg1 >;
310
311 pll4_cfg1: pll4_cfg1 {
312 st,pll_vco = < &pll4_vco_600Mhz >;
313 st,pll_div_pqr = < 11 59 5 >;
314 };
315 };
316};
317
318&rng {
319 status = "okay";
320};
321
322&saes {
323 secure-status = "okay";
324};
325
326&sdmmc1 {
327 pinctrl-names = "default";
328 pinctrl-0 = <&sdmmc1_b4_pins_a>;
329 disable-wp;
330 st,neg-edge;
331 bus-width = <4>;
332 vmmc-supply = <&vdd_sd>;
333 status = "okay";
334};
335
336&uart4 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart4_pins_a>;
339 status = "okay";
340};
341
342&uart8 {
343 pinctrl-names = "default";
344 pinctrl-0 = <&uart8_pins_a>;
345 status = "disabled";
346};
347
348&usart1 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&usart1_pins_a>;
351 uart-has-rtscts;
352 status = "disabled";
353};