| Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef QOS_REG_H |
| 8 | #define QOS_REG_H |
| Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 9 | |
| 10 | #define RCAR_QOS_NONE (3U) |
| 11 | #define RCAR_QOS_TYPE_DEFAULT (0U) |
| 12 | |
| 13 | #define RCAR_DRAM_SPLIT_LINEAR (0U) |
| 14 | #define RCAR_DRAM_SPLIT_4CH (1U) |
| 15 | #define RCAR_DRAM_SPLIT_2CH (2U) |
| 16 | #define RCAR_DRAM_SPLIT_AUTO (3U) |
| 17 | #define RST_BASE (0xE6160000U) |
| 18 | #define RST_MODEMR (RST_BASE + 0x0060U) |
| 19 | |
| 20 | #define DBSC_BASE (0xE6790000U) |
| 21 | #define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U) |
| 22 | #define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) |
| 23 | #define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) |
| 24 | #define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) |
| 25 | #define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) |
| 26 | #define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) |
| 27 | #define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) |
| 28 | #define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U) |
| 29 | #define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U) |
| 30 | #define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U) |
| 31 | #define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU) |
| 32 | #define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U) |
| 33 | #define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U) |
| 34 | #define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U) |
| 35 | #define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU) |
| 36 | #define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U) |
| 37 | #define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U) |
| 38 | #define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U) |
| 39 | #define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU) |
| 40 | #define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U) |
| 41 | #define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U) |
| 42 | #define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U) |
| 43 | #define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU) |
| 44 | #define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U) |
| 45 | #define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U) |
| 46 | #define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U) |
| 47 | #define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU) |
| 48 | #define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U) |
| 49 | #define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U) |
| 50 | #define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U) |
| 51 | #define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU) |
| 52 | #define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U) |
| 53 | #define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U) |
| 54 | #define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U) |
| 55 | #define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU) |
| 56 | #define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) |
| 57 | |
| 58 | #define AXI_BASE (0xE6784000U) |
| 59 | #define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) |
| 60 | #define AXI_ADSPLCR1 (AXI_BASE + 0x000CU) |
| 61 | #define AXI_ADSPLCR2 (AXI_BASE + 0x0010U) |
| 62 | #define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) |
| 63 | #define AXI_MMCR (AXI_BASE + 0x0300U) |
| 64 | #define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U) |
| 65 | #define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U) |
| 66 | #define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U) |
| 67 | #define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U) |
| 68 | #define ADSPLCR0_SWP (0x0CU) |
| 69 | |
| 70 | #define AXI_TR3CR (0xE67D100CU) |
| 71 | #define AXI_TR4CR (0xE67D1014U) |
| 72 | |
| 73 | #define QOS_BASE0 (0xE67E0000U) |
| 74 | #define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U) |
| 75 | #define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U) |
| 76 | #define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U) |
| 77 | #define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U) |
| 78 | #define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U) |
| 79 | #define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U) |
| 80 | #define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U) |
| 81 | |
| 82 | #define QOS_BASE1 (0xE67F0000U) |
| 83 | #define QOSCTRL_RAS (QOS_BASE1 + 0x0000U) |
| 84 | #define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U) |
| 85 | #define QOSCTRL_DANN (QOS_BASE1 + 0x0030U) |
| 86 | #define QOSCTRL_DANT (QOS_BASE1 + 0x0038U) |
| 87 | #define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U) |
| 88 | #define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U) |
| 89 | #define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U) |
| 90 | |
| 91 | #define GPU_ACT_GRD (0xFD820808U) |
| 92 | #define GPU_ACT0 (0xFD820800U) |
| 93 | #define GPU_ACT1 (0xFD821800U) |
| 94 | #define GPU_ACT2 (0xFD822800U) |
| 95 | #define GPU_ACT3 (0xFD823800U) |
| 96 | #define GPU_ACT4 (0xFD824800U) |
| 97 | #define GPU_ACT5 (0xFD825800U) |
| 98 | #define GPU_ACT6 (0xFD826800U) |
| 99 | #define GPU_ACT7 (0xFD827800U) |
| 100 | |
| 101 | #define RT_ACT0 (0xFFC50800U) |
| 102 | #define RT_ACT1 (0xFFC51800U) |
| 103 | |
| 104 | #define CPU_ACT0 (0xF1300800U) |
| 105 | #define CPU_ACT1 (0xF1340800U) |
| 106 | #define CPU_ACT2 (0xF1380800U) |
| 107 | #define CPU_ACT3 (0xF13C0800U) |
| 108 | |
| 109 | #define RCAR_REWT_TRAINING_DISABLE (0U) |
| 110 | #define RCAR_REWT_TRAINING_ENABLE (1U) |
| 111 | |
| 112 | #define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U) |
| 113 | #define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U) |
| 114 | #define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U) |
| 115 | #define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U) |
| 116 | #define QOSWT_WTEN (QOS_BASE0 + 0x8030U) |
| 117 | #define QOSWT_WTREF (QOS_BASE0 + 0x8034U) |
| 118 | #define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U) |
| 119 | #define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU) |
| 120 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 121 | #endif /* QOS_REG_H */ |