blob: 2606d1bee8d96da0f5af3fd48c48d79c126536cf [file] [log] [blame]
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +00001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +00005 */
6
7#ifndef __TZC_DMC500_H__
8#define __TZC_DMC500_H__
9
10#include <tzc_common.h>
11
12#define SI_STATUS_OFFSET 0x000
13#define SI_STATE_CTRL_OFFSET 0x030
14#define SI_FLUSH_CTRL_OFFSET 0x034
15#define SI_INT_CONTROL_OFFSET 0x048
16
17#define SI_INT_STATUS_OFFSET 0x004
18#define SI_TZ_FAIL_ADDRESS_LOW_OFFSET 0x008
19#define SI_TZ_FAIL_ADDRESS_HIGH_OFFSET 0x00c
20#define SI_FAIL_CONTROL_OFFSET 0x010
21#define SI_FAIL_ID_OFFSET 0x014
22#define SI_INT_CLR_OFFSET 0x04c
23
24/*
25 * DMC-500 has 2 system interfaces each having a similar set of regs
26 * to configure each interface.
27 */
28#define SI0_BASE 0x0000
29#define SI1_BASE 0x0200
30
31/* Bit positions of SIx_SI_STATUS */
32#define SI_EMPTY_SHIFT 0x01
33#define SI_STALL_ACK_SHIFT 0x00
34#define SI_EMPTY_MASK 0x01
35#define SI_STALL_ACK_MASK 0x01
36
37/* Bit positions of SIx_SI_INT_STATUS */
38#define PMU_REQ_INT_OVERFLOW_STATUS_SHIFT 18
39#define FAILED_ACCESS_INT_OVERFLOW_STATUS_SHIFT 16
40#define PMU_REQ_INT_STATUS_SHIFT 2
41#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_SHIFT 1
42#define FAILED_ACCESS_INT_STATUS_SHIFT 0
43#define PMU_REQ_INT_OVERFLOW_STATUS_MASK 0x1
44#define FAILED_ACCESS_INT_OVERFLOW_STATUS_MASK 0x1
45#define PMU_REQ_INT_STATUS_MASK 0x1
46#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_MASK 0x1
47#define FAILED_ACCESS_INT_STATUS_MASK 0x1
48
49/* Bit positions of SIx_TZ_FAIL_CONTROL */
50#define DIRECTION_SHIFT 24
51#define NON_SECURE_SHIFT 21
52#define PRIVILEGED_SHIFT 20
53#define FAILED_ACCESS_INT_INFO_RANK_MASKED_SHIFT 3
54#define FAILED_ACCESS_INT_INFO_UNMAPPED_SHIFT 2
55#define FAILED_ACCESS_INT_TZ_FAIL_SHIFT 0x1
56#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_SHIFT 0
57#define DIRECTION_MASK 0x1
58#define NON_SECURE_MASK 0x1
59#define PRIVILEGED_MASK 0x1
60#define FAILED_ACCESS_INT_INFO_RANK_MASKED_MASK 0x1
61#define FAILED_ACCESS_INT_INFO_UNMAPPED_MASK 0x1
62#define FAILED_ACCESS_INT_TZ_FAIL_MASK 1
63#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_MASK 0x1
64
65/* Bit positions of SIx_FAIL_STATUS */
66#define FAIL_ID_VNET_SHIFT 24
67#define FAIL_ID_ID_SHIFT 0
68#define FAIL_ID_VNET_MASK 0xf
69#define FAIL_ID_ID_MASK 0xffffff
70
71/* Bit positions of SIx_SI_STATE_CONTRL */
72#define SI_STALL_REQ_GO 0x0
73#define SI_STALL_REQ_STALL 0x1
74
75/* Bit positions of SIx_SI_FLUSH_CONTROL */
76#define SI_FLUSH_REQ_INACTIVE 0x0
77#define SI_FLUSH_REQ_ACTIVE 0x1
78#define SI_FLUSH_REQ_MASK 0x1
79
80/* Bit positions of SIx_SI_INT_CONTROL */
81#define PMU_REQ_INT_EN_SHIFT 2
82#define OVERLAP_DETECT_INT_EN_SHIFT 1
83#define FAILED_ACCESS_INT_EN_SHIFT 0
84#define PMU_REQ_INT_EN_MASK 0x1
85#define OVERLAP_DETECT_INT_EN_MASK 0x1
86#define FAILED_ACCESS_INT_EN_MASK 0x1
87#define PMU_REQ_INT_EN 0x1
88#define OVERLAP_DETECT_INT_EN 0x1
89#define FAILED_ACCESS_INT_EN 0x1
90
91/* Bit positions of SIx_SI_INT_CLR */
92#define PMU_REQ_OFLOW_CLR_SHIFT 18
93#define FAILED_ACCESS_OFLOW_CLR_SHIFT 16
94#define PMU_REQ_INT_CLR_SHIFT 2
95#define FAILED_ACCESS_INT_CLR_SHIFT 0
96#define PMU_REQ_OFLOW_CLR_MASK 0x1
97#define FAILED_ACCESS_OFLOW_CLR_MASK 0x1
98#define PMU_REQ_INT_CLR_MASK 0x1
99#define FAILED_ACCESS_INT_CLR_MASK 0x1
100#define PMU_REQ_OFLOW_CLR 0x1
101#define FAILED_ACCESS_OFLOW_CLR 0x1
102#define PMU_REQ_INT_CLR 0x1
103#define FAILED_ACCESS_INT_CLR 0x1
104
105/* Macro to get the correct base register for a system interface */
106#define IFACE_OFFSET(sys_if) ((sys_if) ? SI1_BASE : SI0_BASE)
107
108#define MAX_SYS_IF_COUNT 2
109#define MAX_REGION_VAL 8
110
111/* DMC-500 supports striping across a max of 4 DMC instances */
112#define MAX_DMC_COUNT 4
113
114/* Consist of part_number_1 and part_number_0 */
115#define DMC500_PERIPHERAL_ID 0x0450
116
117/* Filter enable bits in a TZC */
118#define TZC_DMC500_REGION_ATTR_F_EN_MASK 0x1
119
120/* Length of registers for configuring each region */
121#define TZC_DMC500_REGION_SIZE 0x018
122
123#ifndef __ASSEMBLY__
124
125#include <stdint.h>
126
127/*
128 * Contains the base addresses of all the DMC instances.
129 */
130typedef struct tzc_dmc500_driver_data {
131 uintptr_t dmc_base[MAX_DMC_COUNT];
132 int dmc_count;
133} tzc_dmc500_driver_data_t;
134
135void tzc_dmc500_driver_init(const tzc_dmc500_driver_data_t *plat_driver_data);
136void tzc_dmc500_configure_region0(tzc_region_attributes_t sec_attr,
137 unsigned int nsaid_permissions);
138void tzc_dmc500_configure_region(int region_no,
Yatharth Kocharfc719752016-04-08 14:40:44 +0100139 unsigned long long region_base,
140 unsigned long long region_top,
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +0000141 tzc_region_attributes_t sec_attr,
142 unsigned int nsaid_permissions);
143void tzc_dmc500_set_action(tzc_action_t action);
144void tzc_dmc500_config_complete(void);
145int tzc_dmc500_verify_complete(void);
146
147
148#endif /* __ASSEMBLY__ */
149#endif /* __TZC_DMC500_H__ */
150