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git01.mediatek.com / filogic / atf / 073fefec8ecb84d862449d86c480f7d52cb66c31 / . / plat / nvidia / tegra / soc / t186 / drivers / include / t18x_ari.h
blob: 8c6f30c8ad875df5ad33578840983faddbe5ddfb [file] [log] [blame]
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]1/*
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]5 */
6
7#ifndef T18X_TEGRA_ARI_H
8#define T18X_TEGRA_ARI_H
9
10/*
11 * ----------------------------------------------------------------------------
12 * t18x_ari.h
13 *
14 * Global ARI definitions.
15 * ----------------------------------------------------------------------------
16 */
17
18enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]19 TEGRA_ARI_VERSION_MAJOR = 3U,
20 TEGRA_ARI_VERSION_MINOR = 1U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]21};
22
23typedef enum {
24 /* indexes below get the core lock */
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]25 TEGRA_ARI_MISC = 0U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]26 /* index 1 is deprecated */
27 /* index 2 is deprecated */
28 /* index 3 is deprecated */
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]29 TEGRA_ARI_ONLINE_CORE = 4U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]30
31 /* indexes below need cluster lock */
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]32 TEGRA_ARI_MISC_CLUSTER = 41U,
33 TEGRA_ARI_IS_CCX_ALLOWED = 42U,
34 TEGRA_ARI_CC3_CTRL = 43U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]35
36 /* indexes below need ccplex lock */
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]37 TEGRA_ARI_ENTER_CSTATE = 80U,
38 TEGRA_ARI_UPDATE_CSTATE_INFO = 81U,
39 TEGRA_ARI_IS_SC7_ALLOWED = 82U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]40 /* index 83 is deprecated */
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]41 TEGRA_ARI_PERFMON = 84U,
42 TEGRA_ARI_UPDATE_CCPLEX_GSC = 85U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]43 /* index 86 is depracated */
44 /* index 87 is deprecated */
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]45 TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88U,
46 TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89U,
47 TEGRA_ARI_MISC_CCPLEX = 90U,
48 TEGRA_ARI_MCA = 91U,
49 TEGRA_ARI_UPDATE_CROSSOVER = 92U,
50 TEGRA_ARI_CSTATE_STATS = 93U,
51 TEGRA_ARI_WRITE_CSTATE_STATS = 94U,
52 TEGRA_ARI_COPY_MISCREG_AA64_RST = 95U,
53 TEGRA_ARI_ROC_CLEAN_CACHE_ONLY = 96U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]54} tegra_ari_req_id_t;
55
56typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]57 TEGRA_ARI_MISC_ECHO = 0U,
58 TEGRA_ARI_MISC_VERSION = 1U,
59 TEGRA_ARI_MISC_FEATURE_LEAF_0 = 2U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]60} tegra_ari_misc_index_t;
61
62typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]63 TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF = 0U,
64 TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT = 1U,
65 TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL = 2U,
66 TEGRA_ARI_MISC_CCPLEX_EDBGREQ = 3U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]67} tegra_ari_misc_ccplex_index_t;
68
69typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]70 TEGRA_ARI_CORE_C0 = 0U,
71 TEGRA_ARI_CORE_C1 = 1U,
72 TEGRA_ARI_CORE_C6 = 6U,
73 TEGRA_ARI_CORE_C7 = 7U,
74 TEGRA_ARI_CORE_WARMRSTREQ = 8U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]75} tegra_ari_core_sleep_state_t;
76
77typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]78 TEGRA_ARI_CLUSTER_CC0 = 0U,
79 TEGRA_ARI_CLUSTER_CC1 = 1U,
80 TEGRA_ARI_CLUSTER_CC6 = 6U,
81 TEGRA_ARI_CLUSTER_CC7 = 7U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]82} tegra_ari_cluster_sleep_state_t;
83
84typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]85 TEGRA_ARI_CCPLEX_CCP0 = 0U,
86 TEGRA_ARI_CCPLEX_CCP1 = 1U,
87 TEGRA_ARI_CCPLEX_CCP3 = 3U, /* obsoleted */
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]88} tegra_ari_ccplex_sleep_state_t;
89
90typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]91 TEGRA_ARI_SYSTEM_SC0 = 0U,
92 TEGRA_ARI_SYSTEM_SC1 = 1U, /* obsoleted */
93 TEGRA_ARI_SYSTEM_SC2 = 2U, /* obsoleted */
94 TEGRA_ARI_SYSTEM_SC3 = 3U, /* obsoleted */
95 TEGRA_ARI_SYSTEM_SC4 = 4U, /* obsoleted */
96 TEGRA_ARI_SYSTEM_SC7 = 7U,
97 TEGRA_ARI_SYSTEM_SC8 = 8U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]98} tegra_ari_system_sleep_state_t;
99
100typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]101 TEGRA_ARI_CROSSOVER_C1_C6 = 0U,
102 TEGRA_ARI_CROSSOVER_CC1_CC6 = 1U,
103 TEGRA_ARI_CROSSOVER_CC1_CC7 = 2U,
104 TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3U, /* obsoleted */
105 TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4U, /* obsoleted */
106 TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5U, /* obsoleted */
107 TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6U, /* obsoleted */
108 TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7U, /* obsoleted */
109 TEGRA_ARI_CROSSOVER_SC0_SC7 = 7U,
110 TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8U, /* obsoleted */
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]111} tegra_ari_crossover_index_t;
112
113typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]114 TEGRA_ARI_CSTATE_STATS_CLEAR = 0U,
115 TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES = 1U,
116 TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, /* obsoleted */
117 TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, /* obsoleted */
118 TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, /* obsoleted */
119 TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, /* obsoleted */
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]120 TEGRA_ARI_CSTATE_STATS_A57_CC6_ENTRIES,
121 TEGRA_ARI_CSTATE_STATS_A57_CC7_ENTRIES,
122 TEGRA_ARI_CSTATE_STATS_D15_CC6_ENTRIES,
123 TEGRA_ARI_CSTATE_STATS_D15_CC7_ENTRIES,
124 TEGRA_ARI_CSTATE_STATS_D15_0_C6_ENTRIES,
125 TEGRA_ARI_CSTATE_STATS_D15_1_C6_ENTRIES,
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]126 TEGRA_ARI_CSTATE_STATS_D15_0_C7_ENTRIES = 14U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]127 TEGRA_ARI_CSTATE_STATS_D15_1_C7_ENTRIES,
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]128 TEGRA_ARI_CSTATE_STATS_A57_0_C7_ENTRIES = 18U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]129 TEGRA_ARI_CSTATE_STATS_A57_1_C7_ENTRIES,
130 TEGRA_ARI_CSTATE_STATS_A57_2_C7_ENTRIES,
131 TEGRA_ARI_CSTATE_STATS_A57_3_C7_ENTRIES,
132 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0,
133 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1,
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]134 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 26U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]135 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1,
136 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2,
137 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3,
138} tegra_ari_cstate_stats_index_t;
139
140typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]141 TEGRA_ARI_GSC_ALL = 0U,
142 TEGRA_ARI_GSC_BPMP = 6U,
143 TEGRA_ARI_GSC_APE = 7U,
144 TEGRA_ARI_GSC_SPE = 8U,
145 TEGRA_ARI_GSC_SCE = 9U,
146 TEGRA_ARI_GSC_APR = 10U,
147 TEGRA_ARI_GSC_TZRAM = 11U,
148 TEGRA_ARI_GSC_SE = 12U,
149 TEGRA_ARI_GSC_BPMP_TO_SPE = 16U,
150 TEGRA_ARI_GSC_SPE_TO_BPMP = 17U,
151 TEGRA_ARI_GSC_CPU_TZ_TO_BPMP = 18U,
152 TEGRA_ARI_GSC_BPMP_TO_CPU_TZ = 19U,
153 TEGRA_ARI_GSC_CPU_NS_TO_BPMP = 20U,
154 TEGRA_ARI_GSC_BPMP_TO_CPU_NS = 21U,
155 TEGRA_ARI_GSC_IPC_SE_SPE_SCE_BPMP = 22U,
156 TEGRA_ARI_GSC_SC7_RESUME_FW = 23U,
157 TEGRA_ARI_GSC_TZ_DRAM_IDX = 34U,
158 TEGRA_ARI_GSC_VPR_IDX = 35U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]159} tegra_ari_gsc_index_t;
160
161/* This macro will produce enums for __name##_LSB, __name##_MSB and __name##_MSK */
162#define TEGRA_ARI_ENUM_MASK_LSB_MSB(__name, __lsb, __msb) __name##_LSB = __lsb, __name##_MSB = __msb
163
164typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]165 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE, 0U, 2U),
166 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE_PRESENT, 7U, 7U),
167 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE, 8U, 9U),
168 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE_PRESENT, 15U, 15U),
169 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE, 16U, 19U),
170 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__IGNORE_CROSSOVERS, 22U, 22U),
171 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE_PRESENT, 23U, 23U),
172 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__WAKE_MASK_PRESENT, 31U, 31U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]173} tegra_ari_update_cstate_info_bitmasks_t;
174
175typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]176 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL__EN, 0U, 0U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]177} tegra_ari_misc_ccplex_bitmasks_t;
178
179typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]180 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_FREQ, 0U, 8U),
181 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_VOLT, 16U, 23U),
182 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__ENABLE, 31U, 31U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]183} tegra_ari_cc3_ctrl_bitmasks_t;
184
185typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]186 TEGRA_ARI_MCA_NOP = 0U,
187 TEGRA_ARI_MCA_READ_SERR = 1U,
188 TEGRA_ARI_MCA_WRITE_SERR = 2U,
189 TEGRA_ARI_MCA_CLEAR_SERR = 4U,
190 TEGRA_ARI_MCA_REPORT_SERR = 5U,
191 TEGRA_ARI_MCA_READ_INTSTS = 6U,
192 TEGRA_ARI_MCA_WRITE_INTSTS = 7U,
193 TEGRA_ARI_MCA_READ_PREBOOT_SERR = 8U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]194} tegra_ari_mca_commands_t;
195
196typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]197 TEGRA_ARI_MCA_RD_WR_DPMU = 0U,
198 TEGRA_ARI_MCA_RD_WR_IOB = 1U,
199 TEGRA_ARI_MCA_RD_WR_MCB = 2U,
200 TEGRA_ARI_MCA_RD_WR_CCE = 3U,
201 TEGRA_ARI_MCA_RD_WR_CQX = 4U,
202 TEGRA_ARI_MCA_RD_WR_CTU = 5U,
203 TEGRA_ARI_MCA_RD_WR_JSR_MTS = 7U,
204 TEGRA_ARI_MCA_RD_BANK_INFO = 0x0fU,
205 TEGRA_ARI_MCA_RD_BANK_TEMPLATE = 0x10U,
206 TEGRA_ARI_MCA_RD_WR_SECURE_ACCESS_REGISTER = 0x11U,
207 TEGRA_ARI_MCA_RD_WR_GLOBAL_CONFIG_REGISTER = 0x12U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]208} tegra_ari_mca_rd_wr_indexes_t;
209
210typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]211 TEGRA_ARI_MCA_RD_WR_ASERRX_CTRL = 0U,
212 TEGRA_ARI_MCA_RD_WR_ASERRX_STATUS = 1U,
213 TEGRA_ARI_MCA_RD_WR_ASERRX_ADDR = 2U,
214 TEGRA_ARI_MCA_RD_WR_ASERRX_MISC1 = 3U,
215 TEGRA_ARI_MCA_RD_WR_ASERRX_MISC2 = 4U,
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]216} tegra_ari_mca_read_asserx_subindexes_t;
217
218typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]219 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_SETTING_ENABLES_NS_PERMITTED, 0U, 0U),
220 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_READING_STATUS_NS_PERMITTED, 1U, 1U),
221 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_PENDING_MCA_ERRORS_NS_PERMITTED, 2U, 2U),
222 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_CLEARING_MCA_INTERRUPTS_NS_PERMITTED, 3U, 3U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]223} tegra_ari_mca_secure_register_bitmasks_t;
224
225typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]226 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_SERR_ERR_CODE, 0U, 15U),
227 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM_ERR, 16U, 16U),
228 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_CRAB_ERR, 17U, 17U),
229 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_RD_WR_N, 18U, 18U),
230 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UCODE_ERR, 19U, 19U),
231 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM, 20U, 23U),
232 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_AV, 58U, 58U),
233 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_MV, 59U, 59U),
234 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_EN, 60U, 60U),
235 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UC, 61U, 61U),
236 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_OVF, 62U, 62U),
237 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_VAL, 63U, 63U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]238
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]239 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_ADDR, 0U, 41U),
240 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_UCODE_ERRCD, 42U, 52U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]241
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]242 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_PWM_ERR, 0U, 0U),
243 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_CRAB_ERR, 1U, 1U),
244 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_UCODE_ERR, 3U, 3U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]245} tegra_ari_mca_aserr0_bitmasks_t;
246
247typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]248 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_SERR_ERR_CODE, 0U, 15U),
249 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MSI_ERR, 16U, 16U),
250 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_IHI_ERR, 17U, 17U),
251 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CRI_ERR, 18U, 18U),
252 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MMCRAB_ERR, 19U, 19U),
253 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CSI_ERR, 20U, 20U),
254 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RD_WR_N, 21U, 21U),
255 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_REQ_ERRT, 22U, 23U),
256 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RESP_ERRT, 24U, 25U),
257 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AV, 58U, 58U),
258 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MV, 59U, 59U),
259 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_EN, 60U, 60U),
260 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_UC, 61U, 61U),
261 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_OVF, 62U, 62U),
262 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_VAL, 63U, 63U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]263
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]264 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AXI_ID, 0U, 7U),
265 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_ID, 8U, 27U),
266 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CID, 28U, 31U),
267 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CMD, 32U, 35U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]268
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]269 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MSI_ERR, 0U, 0U),
270 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_IHI_ERR, 1U, 1U),
271 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CRI_ERR, 2U, 2U),
272 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MMCRAB_ERR, 3U, 3U),
273 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CSI_ERR, 4U, 4U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]274
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]275 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_MISC_ADDR, 0U, 41U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]276} tegra_ari_mca_aserr1_bitmasks_t;
277
278typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]279 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SERR_ERR_CODE, 0U, 15U),
280 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MC_ERR, 16U, 16U),
281 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SYSRAM_ERR, 17U, 17U),
282 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_CLIENT_ID, 18U, 19U),
283 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_AV, 58U, 58U),
284 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MV, 59U, 59U),
285 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_EN, 60U, 60U),
286 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_UC, 61U, 61U),
287 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_OVF, 62U, 62U),
288 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_VAL, 63U, 63U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]289
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]290 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ID, 0U, 17U),
291 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_CMD, 18U, 21U),
292 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ADDR, 22U, 53U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]293
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]294 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_CTRL_EN_MC_ERR, 0U, 0U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]295} tegra_ari_mca_aserr2_bitmasks_t;
296
297typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]298 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_SERR_ERR_CODE, 0U, 15U),
299 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_TO_ERR, 16U, 16U),
300 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_STAT_ERR, 17U, 17U),
301 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_DST_ERR, 18U, 18U),
302 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UNC_ERR, 19U, 19U),
303 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MH_ERR, 20U, 20U),
304 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PERR, 21U, 21U),
305 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PSN_ERR, 22U, 22U),
306 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_AV, 58U, 58U),
307 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MV, 59U, 59U),
308 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_EN, 60U, 60U),
309 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UC, 61U, 61U),
310 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_OVF, 62U, 62U),
311 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_VAL, 63U, 63U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]312
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]313 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_CMD, 0U, 5U),
314 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_ADDR, 6U, 47U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]315
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]316 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TO, 0U, 0U),
317 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_DIV4, 1U, 1U),
318 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TLIMIT, 2U, 11U),
319 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_PSN_ERR_CORR_MSK, 12U, 25U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]320
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]321 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_MORE_INFO, 0U, 17U),
322 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TO_INFO, 18U, 43U),
323 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_SRC, 44U, 45U),
324 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TID, 46U, 52U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]325
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]326 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_TO_ERR, 0U, 0U),
327 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_STAT_ERR, 1U, 1U),
328 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_DST_ERR, 2U, 2U),
329 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_UNC_ERR, 3U, 3U),
330 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_MH_ERR, 4U, 4U),
331 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PERR, 5U, 5U),
332 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PSN_ERR, 6U, 19U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]333} tegra_ari_mca_aserr3_bitmasks_t;
334
335typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]336 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SERR_ERR_CODE, 0U, 15U),
337 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SRC_ERR, 16U, 16U),
338 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_DST_ERR, 17U, 17U),
339 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_REQ_ERR, 18U, 18U),
340 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_RSP_ERR, 19U, 19U),
341 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_AV, 58U, 58U),
342 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_MV, 59U, 59U),
343 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_EN, 60U, 60U),
344 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_UC, 61U, 61U),
345 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_OVF, 62U, 62U),
346 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_VAL, 63U, 63U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]347
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]348 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_CTRL_EN_CPE_ERR, 0U, 0U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]349} tegra_ari_mca_aserr4_bitmasks_t;
350
351typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]352 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_SERR_ERR_CODE, 0U, 15U),
353 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_CTUPAR, 16U, 16U),
354 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MULTI, 17U, 17U),
355 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_AV, 58U, 58U),
356 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MV, 59U, 59U),
357 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_EN, 60U, 60U),
358 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_UC, 61U, 61U),
359 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_OVF, 62U, 62U),
360 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_VAL, 63U, 63U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]361
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]362 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_SRC, 0U, 7U),
363 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ID, 8U, 15U),
364 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_DATA, 16U, 26U),
365 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_CMD, 32U, 35U),
366 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ADDR, 36U, 45U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]367
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]368 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_CTRL_EN_CTUPAR, 0U, 0U),
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]369} tegra_ari_mca_aserr5_bitmasks_t;
370
Varun Wadekar4cc07ae2017-01-04 10:52:54 -0800[diff] [blame]371typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]372 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_SERR_ERR_CODE, 0U, 15U),
373 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_AV, 58U, 58U),
374 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_MV, 59U, 59U),
375 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_EN, 60U, 60U),
376 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_UC, 61U, 61U),
377 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_OVF, 62U, 62U),
378 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_VAL, 63U, 63U),
379
380 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_ADDR_TBD_INFO, 0U, 63U),
Varun Wadekar4cc07ae2017-01-04 10:52:54 -0800[diff] [blame]381} tegra_ari_mca_serr1_bitmasks_t;
382
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]383#undef TEGRA_ARI_ENUM_MASK_LSB_MSB
384
385typedef enum {
Anthony Zhou59fd6152017-03-13 15:34:08 +0800[diff] [blame]386 TEGRA_NVG_CHANNEL_PMIC = 0U,
387 TEGRA_NVG_CHANNEL_POWER_PERF = 1U,
388 TEGRA_NVG_CHANNEL_POWER_MODES = 2U,
389 TEGRA_NVG_CHANNEL_WAKE_TIME = 3U,
390 TEGRA_NVG_CHANNEL_CSTATE_INFO = 4U,
391 TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5U,
392 TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6U,
393 TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7U,
394 TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8U, /* obsoleted */
395 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9U, /* obsoleted */
396 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10U, /* obsoleted */
397 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11U, /* obsoleted */
398 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12U, /* obsoleted */
399 TEGRA_NVG_CHANNEL_CROSSOVER_SC0_SC7 = 12U,
400 TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13U,
401 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14U,
402 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15U, /* obsoleted */
403 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16U, /* obsoleted */
404 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17U, /* obsoleted */
405 TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18U, /* obsoleted */
406 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19U,
407 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20U,
408 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21U,
409 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC7_ENTRIES = 22U,
410 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C6_ENTRIES = 23U,
411 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C6_ENTRIES = 24U,
412 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C6_ENTRIES = 25U, /* Reserved (for Denver15 core 2) */
413 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C6_ENTRIES = 26U, /* Reserved (for Denver15 core 3) */
414 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C7_ENTRIES = 27U,
415 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C7_ENTRIES = 28U,
416 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C7_ENTRIES = 29U, /* Reserved (for Denver15 core 2) */
417 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C7_ENTRIES = 30U, /* Reserved (for Denver15 core 3) */
418 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_0_C7_ENTRIES = 31U,
419 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_1_C7_ENTRIES = 32U,
420 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_2_C7_ENTRIES = 33U,
421 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34U,
422 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35U,
423 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36U,
424 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37U, /* Reserved (for Denver15 core 2) */
425 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38U, /* Reserved (for Denver15 core 3) */
426 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39U,
427 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40U,
428 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2 = 41U,
429 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3 = 42U,
430 TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43U,
431 TEGRA_NVG_CHANNEL_ONLINE_CORE = 44U,
432 TEGRA_NVG_CHANNEL_CC3_CTRL = 45U,
433 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46U, /* obsoleted */
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]434 TEGRA_NVG_CHANNEL_LAST_INDEX,
435} tegra_nvg_channel_id_t;
436
437#endif /* T18X_TEGRA_ARI_H */