| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <debug.h> |
| 32 | #include <mmio.h> |
| 33 | #include <pmc.h> |
| 34 | #include <tegra_def.h> |
| 35 | |
| 36 | #define SB_CSR 0x0 |
| 37 | #define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) |
| 38 | |
| 39 | /* CPU reset vector */ |
| 40 | #define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */ |
| 41 | #define SB_AA64_RESET_HI 0x34 /* width = 11:0 */ |
| 42 | |
| 43 | extern void tegra_secure_entrypoint(void); |
| 44 | |
| 45 | /******************************************************************************* |
| 46 | * Setup secondary CPU vectors |
| 47 | ******************************************************************************/ |
| 48 | void plat_secondary_setup(void) |
| 49 | { |
| 50 | uint32_t val; |
| 51 | uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; |
| 52 | |
| 53 | INFO("Setting up secondary CPU boot\n"); |
| 54 | |
| 55 | /* setup secondary CPU vector */ |
| 56 | mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW, |
| 57 | (reset_addr & 0xFFFFFFFF) | 1); |
| 58 | val = reset_addr >> 32; |
| 59 | mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF); |
| 60 | |
| 61 | /* configure PMC */ |
| 62 | tegra_pmc_cpu_setup(reset_addr); |
| 63 | } |