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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautierf9d40d52019-01-17 14:41:46 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_DEF_H
8#define STM32MP1_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010011#include <drivers/st/stm32mp1_rcc.h>
12#include <dt-bindings/clock/stm32mp1-clks.h>
13#include <dt-bindings/reset/stm32mp1-resets.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils_def.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020016
Yann Gautier57e282b2019-01-07 11:17:24 +010017#ifndef __ASSEMBLY__
Yann Gautierb5d2ed42019-02-14 11:13:50 +010018#include <drivers/st/stm32mp1_clk.h>
19
Yann Gautier57e282b2019-01-07 11:17:24 +010020#include <boot_api.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010021#include <stm32mp_common.h>
22#include <stm32mp_dt.h>
Yann Gautiere4a3c352019-02-14 10:53:33 +010023#include <stm32mp_shres_helpers.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010024#include <stm32mp1_private.h>
25#endif
26
Yann Gautier4b0c72a2018-07-16 10:54:09 +020027/*******************************************************************************
28 * STM32MP1 memory map related constants
29 ******************************************************************************/
30
Yann Gautiera2e2a302019-02-14 11:13:39 +010031#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
32#define STM32MP_SYSRAM_SIZE U(0x00040000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020033
34/* DDR configuration */
Yann Gautiera2e2a302019-02-14 11:13:39 +010035#define STM32MP_DDR_BASE U(0xC0000000)
36#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020037
38/* DDR power initializations */
39#ifndef __ASSEMBLY__
40enum ddr_type {
41 STM32MP_DDR3,
42 STM32MP_LPDDR2,
43};
44#endif
45
46/* Section used inside TF binaries */
Yann Gautiera2e2a302019-02-14 11:13:39 +010047#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020048/* 256 Octets reserved for header */
Yann Gautiera2e2a302019-02-14 11:13:39 +010049#define STM32MP_HEADER_SIZE U(0x00000100)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020050
Yann Gautiera2e2a302019-02-14 11:13:39 +010051#define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \
52 STM32MP_PARAM_LOAD_SIZE + \
53 STM32MP_HEADER_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020054
Yann Gautiera2e2a302019-02-14 11:13:39 +010055#define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \
56 (STM32MP_PARAM_LOAD_SIZE + \
57 STM32MP_HEADER_SIZE))
Yann Gautier4b0c72a2018-07-16 10:54:09 +020058
59#if STACK_PROTECTOR_ENABLED
Yann Gautiera2e2a302019-02-14 11:13:39 +010060#define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020061#else
Yann Gautiera2e2a302019-02-14 11:13:39 +010062#define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020063#endif
64
Yann Gautiera2e2a302019-02-14 11:13:39 +010065#define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \
66 STM32MP_SYSRAM_SIZE - \
67 STM32MP_BL32_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020068
69#if STACK_PROTECTOR_ENABLED
Yann Gautiera2e2a302019-02-14 11:13:39 +010070#define STM32MP_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020071#else
Yann Gautiera2e2a302019-02-14 11:13:39 +010072#define STM32MP_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020073#endif
74
Yann Gautiera2e2a302019-02-14 11:13:39 +010075#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
76 STM32MP_BL2_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020077
78/* BL2 and BL32/sp_min require 5 tables */
79#define MAX_XLAT_TABLES 5
80
81/*
82 * MAX_MMAP_REGIONS is usually:
83 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
84 */
Yann Gautier9d135e42018-07-16 19:36:06 +020085#if defined(IMAGE_BL2)
86 #define MAX_MMAP_REGIONS 11
87#endif
88#if defined(IMAGE_BL32)
89 #define MAX_MMAP_REGIONS 6
90#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +020091
92/* DTB initialization value */
Yann Gautiera2e2a302019-02-14 11:13:39 +010093#define STM32MP_DTB_SIZE U(0x00004000) /* 16Ko for DTB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020094
Yann Gautiera2e2a302019-02-14 11:13:39 +010095#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
96 STM32MP_DTB_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020097
Yann Gautiera2e2a302019-02-14 11:13:39 +010098#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
Yann Gautier4b0c72a2018-07-16 10:54:09 +020099
100/*******************************************************************************
101 * STM32MP1 device/io map related constants (used for MMU)
102 ******************************************************************************/
103#define STM32MP1_DEVICE1_BASE U(0x40000000)
104#define STM32MP1_DEVICE1_SIZE U(0x40000000)
105
106#define STM32MP1_DEVICE2_BASE U(0x80000000)
107#define STM32MP1_DEVICE2_SIZE U(0x40000000)
108
109/*******************************************************************************
110 * STM32MP1 RCC
111 ******************************************************************************/
112#define RCC_BASE U(0x50000000)
113
114/*******************************************************************************
115 * STM32MP1 PWR
116 ******************************************************************************/
117#define PWR_BASE U(0x50001000)
118
119/*******************************************************************************
Yann Gautier038bff22019-01-17 19:17:47 +0100120 * STM32MP1 GPIO
121 ******************************************************************************/
122#define GPIOA_BASE U(0x50002000)
123#define GPIOB_BASE U(0x50003000)
124#define GPIOC_BASE U(0x50004000)
125#define GPIOD_BASE U(0x50005000)
126#define GPIOE_BASE U(0x50006000)
127#define GPIOF_BASE U(0x50007000)
128#define GPIOG_BASE U(0x50008000)
129#define GPIOH_BASE U(0x50009000)
130#define GPIOI_BASE U(0x5000A000)
131#define GPIOJ_BASE U(0x5000B000)
132#define GPIOK_BASE U(0x5000C000)
133#define GPIOZ_BASE U(0x54004000)
134#define GPIO_BANK_OFFSET U(0x1000)
135
136/* Bank IDs used in GPIO driver API */
137#define GPIO_BANK_A U(0)
138#define GPIO_BANK_B U(1)
139#define GPIO_BANK_C U(2)
140#define GPIO_BANK_D U(3)
141#define GPIO_BANK_E U(4)
142#define GPIO_BANK_F U(5)
143#define GPIO_BANK_G U(6)
144#define GPIO_BANK_H U(7)
145#define GPIO_BANK_I U(8)
146#define GPIO_BANK_J U(9)
147#define GPIO_BANK_K U(10)
148#define GPIO_BANK_Z U(25)
149
150#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
151
152/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200153 * STM32MP1 UART
154 ******************************************************************************/
155#define USART1_BASE U(0x5C000000)
156#define USART2_BASE U(0x4000E000)
157#define USART3_BASE U(0x4000F000)
158#define UART4_BASE U(0x40010000)
159#define UART5_BASE U(0x40011000)
160#define USART6_BASE U(0x44003000)
161#define UART7_BASE U(0x40018000)
162#define UART8_BASE U(0x40019000)
Yann Gautiera2e2a302019-02-14 11:13:39 +0100163#define STM32MP_UART_BAUDRATE U(115200)
Yann Gautier038bff22019-01-17 19:17:47 +0100164
165/* For UART crash console */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100166#define STM32MP_DEBUG_USART_BASE UART4_BASE
Yann Gautier038bff22019-01-17 19:17:47 +0100167/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100168#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
Yann Gautier038bff22019-01-17 19:17:47 +0100169#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
170#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
171#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
172#define DEBUG_UART_TX_GPIO_PORT 11
173#define DEBUG_UART_TX_GPIO_ALTERNATE 6
174#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
175#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
176#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
177#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200178
179/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200180 * STM32MP1 TZC (TZ400)
181 ******************************************************************************/
182#define STM32MP1_TZC_BASE U(0x5C006000)
183
184#define STM32MP1_TZC_A7_ID U(0)
Yann Gautiered342322019-02-15 17:33:27 +0100185#define STM32MP1_TZC_M4_ID U(1)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200186#define STM32MP1_TZC_LCD_ID U(3)
187#define STM32MP1_TZC_GPU_ID U(4)
188#define STM32MP1_TZC_MDMA_ID U(5)
189#define STM32MP1_TZC_DMA_ID U(6)
190#define STM32MP1_TZC_USB_HOST_ID U(7)
191#define STM32MP1_TZC_USB_OTG_ID U(8)
192#define STM32MP1_TZC_SDMMC_ID U(9)
193#define STM32MP1_TZC_ETH_ID U(10)
194#define STM32MP1_TZC_DAP_ID U(15)
195
Yann Gautierf9d40d52019-01-17 14:41:46 +0100196#define STM32MP1_FILTER_BIT_ALL U(3)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200197
198/*******************************************************************************
199 * STM32MP1 SDMMC
200 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +0100201#define STM32MP_SDMMC1_BASE U(0x58005000)
202#define STM32MP_SDMMC2_BASE U(0x58007000)
203#define STM32MP_SDMMC3_BASE U(0x48004000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200204
Yann Gautiera2e2a302019-02-14 11:13:39 +0100205#define STM32MP_MMC_INIT_FREQ 400000 /*400 KHz*/
206#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/
207#define STM32MP_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/
208#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/
209#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200210
211/*******************************************************************************
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100212 * STM32MP1 BSEC / OTP
213 ******************************************************************************/
214#define STM32MP1_OTP_MAX_ID 0x5FU
215#define STM32MP1_UPPER_OTP_START 0x20U
216
217#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
218
219/* OTP offsets */
220#define DATA0_OTP U(0)
221
222/* OTP mask */
223/* DATA0 */
224#define DATA0_OTP_SECURED BIT(6)
225
226/*******************************************************************************
Yann Gautier41934662018-07-20 11:36:05 +0200227 * STM32MP1 TAMP
228 ******************************************************************************/
229#define TAMP_BASE U(0x5C00A000)
230#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
231
232#if !(defined(__LINKER__) || defined(__ASSEMBLY__))
233static inline uint32_t tamp_bkpr(uint32_t idx)
234{
235 return TAMP_BKP_REGISTER_BASE + (idx << 2);
236}
237#endif
238
239/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200240 * STM32MP1 DDRCTRL
241 ******************************************************************************/
242#define DDRCTRL_BASE U(0x5A003000)
243
244/*******************************************************************************
245 * STM32MP1 DDRPHYC
246 ******************************************************************************/
247#define DDRPHYC_BASE U(0x5A004000)
248
249/*******************************************************************************
250 * STM32MP1 I2C4
251 ******************************************************************************/
252#define I2C4_BASE U(0x5C002000)
253
Yann Gautier4d429472019-02-14 11:15:20 +0100254/*******************************************************************************
255 * Device Tree defines
256 ******************************************************************************/
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100257#define DT_PWR_COMPAT "st,stm32mp1-pwr"
Yann Gautier4d429472019-02-14 11:15:20 +0100258#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
259
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200260#endif /* STM32MP1_DEF_H */