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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
Joel Hutton5cc3bc82018-03-21 11:40:57 +00002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Tony Xief6118cc2016-01-15 17:17:32 +08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
Tony Xief6118cc2016-01-15 17:17:32 +08007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Tony Xief6118cc2016-01-15 17:17:32 +08009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <common/bl_common.h>
12#include <common/debug.h>
13#include <drivers/console.h>
14#include <drivers/generic_delay_timer.h>
15#include <drivers/ti/uart/uart_16550.h>
16#include <lib/coreboot.h>
17#include <lib/mmio.h>
18#include <plat_private.h>
19#include <plat/common/platform.h>
Tony Xief6118cc2016-01-15 17:17:32 +080020
Tony Xief6118cc2016-01-15 17:17:32 +080021/*
22 * The next 2 constants identify the extents of the code & RO data region.
23 * These addresses are used by the MMU setup code and therefore they must be
24 * page-aligned. It is the responsibility of the linker script to ensure that
25 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
26 */
Joel Hutton5cc3bc82018-03-21 11:40:57 +000027IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE);
28IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT);
Tony Xief6118cc2016-01-15 17:17:32 +080029
Tony Xief6118cc2016-01-15 17:17:32 +080030static entry_point_info_t bl32_ep_info;
31static entry_point_info_t bl33_ep_info;
32
33/*******************************************************************************
34 * Return a pointer to the 'entry_point_info' structure of the next image for
35 * the security state specified. BL33 corresponds to the non-secure image type
36 * while BL32 corresponds to the secure image type. A NULL pointer is returned
37 * if the image does not exist.
38 ******************************************************************************/
39entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
40{
41 entry_point_info_t *next_image_info;
42
43 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
44
45 /* None of the images on this platform can have 0x0 as the entrypoint */
46 if (next_image_info->pc)
47 return next_image_info;
48 else
49 return NULL;
50}
51
tony.xie54973e72017-04-24 16:18:10 +080052#pragma weak params_early_setup
53void params_early_setup(void *plat_param_from_bl2)
54{
55}
56
Tony Xief6118cc2016-01-15 17:17:32 +080057/*******************************************************************************
58 * Perform any BL3-1 early platform setup. Here is an opportunity to copy
John Tsichritzisd653d332018-09-14 10:34:57 +010059 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
Tony Xief6118cc2016-01-15 17:17:32 +080060 * are lost (potentially). This needs to be done before the MMU is initialized
61 * so that the memory layout can be used while creating page tables.
62 * BL2 has flushed this information to memory, so we are guaranteed to pick up
63 * good data.
64 ******************************************************************************/
Antonio Nino Diaz58230902018-09-24 17:16:20 +010065void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
66 u_register_t arg2, u_register_t arg3)
Tony Xief6118cc2016-01-15 17:17:32 +080067{
Julius Wernerf39c8062017-08-02 16:31:04 -070068 static console_16550_t console;
Antonio Nino Diaz58230902018-09-24 17:16:20 +010069 struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
70 void *plat_params_from_bl2 = (void *) arg1;
Julius Wernerf39c8062017-08-02 16:31:04 -070071
Julius Wernerc7087782017-06-09 15:22:44 -070072 params_early_setup(plat_params_from_bl2);
73
74#if COREBOOT
75 if (coreboot_serial.type)
Julius Wernerf39c8062017-08-02 16:31:04 -070076 console_16550_register(coreboot_serial.baseaddr,
77 coreboot_serial.input_hertz,
78 coreboot_serial.baud,
79 &console);
Julius Wernerc7087782017-06-09 15:22:44 -070080#else
Julius Wernerf39c8062017-08-02 16:31:04 -070081 console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK,
82 PLAT_RK_UART_BAUDRATE, &console);
Julius Wernerc7087782017-06-09 15:22:44 -070083#endif
Tony Xief6118cc2016-01-15 17:17:32 +080084
85 VERBOSE("bl31_setup\n");
86
87 /* Passing a NULL context is a critical programming error */
Antonio Nino Diaz58230902018-09-24 17:16:20 +010088 assert(arg_from_bl2);
Tony Xief6118cc2016-01-15 17:17:32 +080089
Antonio Nino Diaz58230902018-09-24 17:16:20 +010090 assert(arg_from_bl2->h.type == PARAM_BL31);
91 assert(arg_from_bl2->h.version >= VERSION_1);
Tony Xief6118cc2016-01-15 17:17:32 +080092
Antonio Nino Diaz58230902018-09-24 17:16:20 +010093 bl32_ep_info = *arg_from_bl2->bl32_ep_info;
94 bl33_ep_info = *arg_from_bl2->bl33_ep_info;
Tony Xief6118cc2016-01-15 17:17:32 +080095}
96
97/*******************************************************************************
98 * Perform any BL3-1 platform setup code
99 ******************************************************************************/
100void bl31_platform_setup(void)
101{
Antonio Nino Diaz2361fcc2016-05-05 15:25:02 +0100102 generic_delay_timer_init();
Tony Xief6118cc2016-01-15 17:17:32 +0800103 plat_rockchip_soc_init();
104
105 /* Initialize the gic cpu and distributor interfaces */
106 plat_rockchip_gic_driver_init();
107 plat_rockchip_gic_init();
108 plat_rockchip_pmu_init();
109}
110
111/*******************************************************************************
112 * Perform the very early platform specific architectural setup here. At the
113 * moment this is only intializes the mmu in a quick and dirty way.
114 ******************************************************************************/
115void bl31_plat_arch_setup(void)
116{
117 plat_cci_init();
118 plat_cci_enable();
119 plat_configure_mmu_el3(BL31_RO_BASE,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900120 BL_COHERENT_RAM_END - BL31_RO_BASE,
Tony Xief6118cc2016-01-15 17:17:32 +0800121 BL31_RO_BASE,
122 BL31_RO_LIMIT,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900123 BL_COHERENT_RAM_BASE,
124 BL_COHERENT_RAM_END);
Tony Xief6118cc2016-01-15 17:17:32 +0800125}