Soby Mathew | 0d268dc | 2016-07-11 14:13:56 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Soby Mathew | 0d268dc | 2016-07-11 14:13:56 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <platform_def.h> |
| 10 | #include "../drivers/pwrc/fvp_pwrc.h" |
| 11 | #include "../fvp_def.h" |
| 12 | |
Yatharth Kochar | f528faf | 2016-06-28 16:58:26 +0100 | [diff] [blame] | 13 | .globl plat_secondary_cold_boot_setup |
Soby Mathew | 0d268dc | 2016-07-11 14:13:56 +0100 | [diff] [blame] | 14 | .globl plat_get_my_entrypoint |
| 15 | .globl plat_is_my_cpu_primary |
| 16 | |
Yatharth Kochar | f528faf | 2016-06-28 16:58:26 +0100 | [diff] [blame] | 17 | /* -------------------------------------------------------------------- |
| 18 | * void plat_secondary_cold_boot_setup (void); |
| 19 | * |
| 20 | * For AArch32, cold-booting secondary CPUs is not yet |
| 21 | * implemented and they panic. |
| 22 | * -------------------------------------------------------------------- |
| 23 | */ |
| 24 | func plat_secondary_cold_boot_setup |
| 25 | cb_panic: |
| 26 | b cb_panic |
| 27 | endfunc plat_secondary_cold_boot_setup |
| 28 | |
Soby Mathew | 0d268dc | 2016-07-11 14:13:56 +0100 | [diff] [blame] | 29 | /* --------------------------------------------------------------------- |
| 30 | * unsigned long plat_get_my_entrypoint (void); |
| 31 | * |
| 32 | * Main job of this routine is to distinguish between a cold and warm |
| 33 | * boot. On FVP, this information can be queried from the power |
| 34 | * controller. The Power Control SYS Status Register (PSYSR) indicates |
| 35 | * the wake-up reason for the CPU. |
| 36 | * |
| 37 | * For a cold boot, return 0. |
| 38 | * For a warm boot, read the mailbox and return the address it contains. |
| 39 | * |
| 40 | * TODO: PSYSR is a common register and should be |
| 41 | * accessed using locks. Since it is not possible |
| 42 | * to use locks immediately after a cold reset |
| 43 | * we are relying on the fact that after a cold |
| 44 | * reset all cpus will read the same WK field |
| 45 | * --------------------------------------------------------------------- |
| 46 | */ |
| 47 | func plat_get_my_entrypoint |
| 48 | /* --------------------------------------------------------------------- |
| 49 | * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC |
| 50 | * WakeRequest signal" then it is a warm boot. |
| 51 | * --------------------------------------------------------------------- |
| 52 | */ |
| 53 | ldcopr r2, MPIDR |
| 54 | ldr r1, =PWRC_BASE |
| 55 | str r2, [r1, #PSYSR_OFF] |
| 56 | ldr r2, [r1, #PSYSR_OFF] |
| 57 | ubfx r2, r2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH |
| 58 | cmp r2, #WKUP_PPONR |
| 59 | beq warm_reset |
| 60 | cmp r2, #WKUP_GICREQ |
| 61 | beq warm_reset |
| 62 | |
| 63 | /* Cold reset */ |
| 64 | mov r0, #0 |
| 65 | bx lr |
| 66 | |
| 67 | warm_reset: |
| 68 | /* --------------------------------------------------------------------- |
| 69 | * A mailbox is maintained in the trusted SRAM. It is flushed out of the |
| 70 | * caches after every update using normal memory so it is safe to read |
| 71 | * it here with SO attributes. |
| 72 | * --------------------------------------------------------------------- |
| 73 | */ |
| 74 | ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE |
| 75 | ldr r0, [r0] |
| 76 | cmp r0, #0 |
| 77 | beq _panic |
| 78 | bx lr |
| 79 | |
| 80 | /* --------------------------------------------------------------------- |
| 81 | * The power controller indicates this is a warm reset but the mailbox |
| 82 | * is empty. This should never happen! |
| 83 | * --------------------------------------------------------------------- |
| 84 | */ |
| 85 | _panic: |
| 86 | b _panic |
| 87 | endfunc plat_get_my_entrypoint |
| 88 | |
| 89 | /* ----------------------------------------------------- |
| 90 | * unsigned int plat_is_my_cpu_primary (void); |
| 91 | * |
| 92 | * Find out whether the current cpu is the primary |
| 93 | * cpu. |
| 94 | * ----------------------------------------------------- |
| 95 | */ |
| 96 | func plat_is_my_cpu_primary |
| 97 | ldcopr r0, MPIDR |
| 98 | ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) |
| 99 | and r0, r1 |
| 100 | cmp r0, #FVP_PRIMARY_CPU |
| 101 | moveq r0, #1 |
| 102 | movne r0, #0 |
| 103 | bx lr |
| 104 | endfunc plat_is_my_cpu_primary |