blob: b3fccdec4e8da23063cbab8c915450a10d705805 [file] [log] [blame]
Soby Mathewec8ac1c2016-05-05 14:32:05 +01001/*
Antonio Nino Diaz4ef91f12017-02-20 14:22:22 +00002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewec8ac1c2016-05-05 14:32:05 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewec8ac1c2016-05-05 14:32:05 +01005 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <bl_common.h>
10#include <context.h>
Yatharth Kochar06460cd2016-06-30 15:02:31 +010011#include <el3_common_macros.S>
Soby Mathewec8ac1c2016-05-05 14:32:05 +010012#include <runtime_svc.h>
13#include <smcc_helpers.h>
14#include <smcc_macros.S>
Antonio Nino Diaz4ef91f12017-02-20 14:22:22 +000015#include <xlat_tables_defs.h>
Soby Mathewec8ac1c2016-05-05 14:32:05 +010016
17 .globl sp_min_vector_table
18 .globl sp_min_entrypoint
19 .globl sp_min_warm_entrypoint
20
Yatharth Kochar06460cd2016-06-30 15:02:31 +010021
22vector_base sp_min_vector_table
Soby Mathewec8ac1c2016-05-05 14:32:05 +010023 b sp_min_entrypoint
24 b plat_panic_handler /* Undef */
25 b handle_smc /* Syscall */
26 b plat_panic_handler /* Prefetch abort */
27 b plat_panic_handler /* Data abort */
28 b plat_panic_handler /* Reserved */
29 b plat_panic_handler /* IRQ */
30 b plat_panic_handler /* FIQ */
Soby Mathewec8ac1c2016-05-05 14:32:05 +010031
Soby Mathewec8ac1c2016-05-05 14:32:05 +010032
33/*
34 * The Cold boot/Reset entrypoint for SP_MIN
35 */
36func sp_min_entrypoint
Yatharth Kochar06460cd2016-06-30 15:02:31 +010037#if !RESET_TO_SP_MIN
38 /* ---------------------------------------------------------------
39 * Preceding bootloader has populated r0 with a pointer to a
40 * 'bl_params_t' structure & r1 with a pointer to platform
41 * specific structure
42 * ---------------------------------------------------------------
Soby Mathewec8ac1c2016-05-05 14:32:05 +010043 */
Yatharth Kochar06460cd2016-06-30 15:02:31 +010044 mov r11, r0
45 mov r12, r1
Soby Mathewec8ac1c2016-05-05 14:32:05 +010046
Yatharth Kochar06460cd2016-06-30 15:02:31 +010047 /* ---------------------------------------------------------------------
48 * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
49 * sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
50 * and primary/secondary CPU logic should not be executed in this case.
51 *
David Cunadofee86532017-04-13 22:38:29 +010052 * Also, assume that the previous bootloader has already initialised the
53 * SCTLR, including the CPU endianness, and has initialised the memory.
Yatharth Kochar06460cd2016-06-30 15:02:31 +010054 * ---------------------------------------------------------------------
Soby Mathewec8ac1c2016-05-05 14:32:05 +010055 */
Yatharth Kochar06460cd2016-06-30 15:02:31 +010056 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +010057 _init_sctlr=0 \
Yatharth Kochar06460cd2016-06-30 15:02:31 +010058 _warm_boot_mailbox=0 \
59 _secondary_cold_boot=0 \
60 _init_memory=0 \
61 _init_c_runtime=1 \
62 _exception_vectors=sp_min_vector_table
Soby Mathewec8ac1c2016-05-05 14:32:05 +010063
Yatharth Kochar06460cd2016-06-30 15:02:31 +010064 /* ---------------------------------------------------------------------
65 * Relay the previous bootloader's arguments to the platform layer
66 * ---------------------------------------------------------------------
Soby Mathewec8ac1c2016-05-05 14:32:05 +010067 */
Yatharth Kochar06460cd2016-06-30 15:02:31 +010068 mov r0, r11
69 mov r1, r12
70#else
71 /* ---------------------------------------------------------------------
72 * For RESET_TO_SP_MIN systems which have a programmable reset address,
73 * sp_min_entrypoint() is executed only on the cold boot path so we can
74 * skip the warm boot mailbox mechanism.
75 * ---------------------------------------------------------------------
Soby Mathewec8ac1c2016-05-05 14:32:05 +010076 */
Yatharth Kochar06460cd2016-06-30 15:02:31 +010077 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +010078 _init_sctlr=1 \
Yatharth Kochar06460cd2016-06-30 15:02:31 +010079 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
80 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
81 _init_memory=1 \
82 _init_c_runtime=1 \
83 _exception_vectors=sp_min_vector_table
Soby Mathewec8ac1c2016-05-05 14:32:05 +010084
Yatharth Kochar06460cd2016-06-30 15:02:31 +010085 /* ---------------------------------------------------------------------
86 * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
87 * to run so there's no argument to relay from a previous bootloader.
88 * Zero the arguments passed to the platform layer to reflect that.
89 * ---------------------------------------------------------------------
Soby Mathewec8ac1c2016-05-05 14:32:05 +010090 */
Yatharth Kochar06460cd2016-06-30 15:02:31 +010091 mov r0, #0
92 mov r1, #0
93#endif /* RESET_TO_SP_MIN */
Soby Mathewec8ac1c2016-05-05 14:32:05 +010094
Soby Mathewec8ac1c2016-05-05 14:32:05 +010095 bl sp_min_early_platform_setup
96 bl sp_min_plat_arch_setup
97
98 /* Jump to the main function */
99 bl sp_min_main
100
101 /* -------------------------------------------------------------
102 * Clean the .data & .bss sections to main memory. This ensures
103 * that any global data which was initialised by the primary CPU
104 * is visible to secondary CPUs before they enable their data
105 * caches and participate in coherency.
106 * -------------------------------------------------------------
107 */
108 ldr r0, =__DATA_START__
109 ldr r1, =__DATA_END__
110 sub r1, r1, r0
111 bl clean_dcache_range
112
113 ldr r0, =__BSS_START__
114 ldr r1, =__BSS_END__
115 sub r1, r1, r0
116 bl clean_dcache_range
117
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100118 bl smc_get_next_ctx
Soby Mathewf3e3a432017-03-30 14:42:54 +0100119
120 /* r0 points to `smc_ctx_t` */
121 /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100122 b sp_min_exit
123endfunc sp_min_entrypoint
124
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100125
126/*
127 * SMC handling function for SP_MIN.
128 */
129func handle_smc
Soby Mathewf3e3a432017-03-30 14:42:54 +0100130 /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
131 str lr, [sp, #SMC_CTX_LR_MON]
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100132
Soby Mathewf3e3a432017-03-30 14:42:54 +0100133 smcc_save_gp_mode_regs
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100134
Soby Mathewadb70272016-12-06 12:10:51 +0000135 /*
Soby Mathewf3e3a432017-03-30 14:42:54 +0100136 * `sp` still points to `smc_ctx_t`. Save it to a register
137 * and restore the C runtime stack pointer to `sp`.
Soby Mathewadb70272016-12-06 12:10:51 +0000138 */
Soby Mathewf3e3a432017-03-30 14:42:54 +0100139 mov r2, sp /* handle */
140 ldr sp, [r2, #SMC_CTX_SP_MON]
141
142 ldr r0, [r2, #SMC_CTX_SCR]
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100143 and r3, r0, #SCR_NS_BIT /* flags */
144
145 /* Switch to Secure Mode*/
146 bic r0, #SCR_NS_BIT
147 stcopr r0, SCR
148 isb
Soby Mathewf3e3a432017-03-30 14:42:54 +0100149
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100150 ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */
151 /* Check whether an SMC64 is issued */
152 tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT)
Soby Mathewf3e3a432017-03-30 14:42:54 +0100153 beq 1f
154 /* SMC32 is not detected. Return error back to caller */
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100155 mov r0, #SMC_UNK
156 str r0, [r2, #SMC_CTX_GPREG_R0]
157 mov r0, r2
Soby Mathewf3e3a432017-03-30 14:42:54 +0100158 b sp_min_exit
Yatharth Kochar06460cd2016-06-30 15:02:31 +01001591:
Soby Mathewf3e3a432017-03-30 14:42:54 +0100160 /* SMC32 is detected */
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100161 mov r1, #0 /* cookie */
162 bl handle_runtime_svc
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100163
Soby Mathewf3e3a432017-03-30 14:42:54 +0100164 /* `r0` points to `smc_ctx_t` */
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100165 b sp_min_exit
166endfunc handle_smc
167
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100168/*
169 * The Warm boot entrypoint for SP_MIN.
170 */
171func sp_min_warm_entrypoint
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100172 /*
173 * On the warm boot path, most of the EL3 initialisations performed by
174 * 'el3_entrypoint_common' must be skipped:
175 *
176 * - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by
David Cunadofee86532017-04-13 22:38:29 +0100177 * programming the reset address do we need to initialied the SCTLR.
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100178 * In other cases, we assume this has been taken care by the
179 * entrypoint code.
180 *
181 * - No need to determine the type of boot, we know it is a warm boot.
182 *
183 * - Do not try to distinguish between primary and secondary CPUs, this
184 * notion only exists for a cold boot.
185 *
186 * - No need to initialise the memory or the C runtime environment,
187 * it has been done once and for all on the cold boot path.
188 */
189 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100190 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100191 _warm_boot_mailbox=0 \
192 _secondary_cold_boot=0 \
193 _init_memory=0 \
194 _init_c_runtime=0 \
195 _exception_vectors=sp_min_vector_table
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100196
Jeenu Viswambharan46144962017-01-05 10:37:21 +0000197 /*
198 * We're about to enable MMU and participate in PSCI state coordination.
199 *
200 * The PSCI implementation invokes platform routines that enable CPUs to
201 * participate in coherency. On a system where CPUs are not
Soby Mathew043fe9c2017-04-10 22:35:42 +0100202 * cache-coherent without appropriate platform specific programming,
203 * having caches enabled until such time might lead to coherency issues
204 * (resulting from stale data getting speculatively fetched, among
205 * others). Therefore we keep data caches disabled even after enabling
206 * the MMU for such platforms.
Jeenu Viswambharan46144962017-01-05 10:37:21 +0000207 *
Soby Mathew043fe9c2017-04-10 22:35:42 +0100208 * On systems with hardware-assisted coherency, or on single cluster
209 * platforms, such platform specific programming is not required to
210 * enter coherency (as CPUs already are); and there's no reason to have
211 * caches disabled either.
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100212 */
213 mov r0, #DISABLE_DCACHE
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100214 bl bl32_plat_enable_mmu
215
Soby Mathew043fe9c2017-04-10 22:35:42 +0100216#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
217 ldcopr r0, SCTLR
218 orr r0, r0, #SCTLR_C_BIT
219 stcopr r0, SCTLR
220 isb
221#endif
222
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100223 bl sp_min_warm_boot
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100224 bl smc_get_next_ctx
Soby Mathewf3e3a432017-03-30 14:42:54 +0100225 /* r0 points to `smc_ctx_t` */
226 /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100227 b sp_min_exit
228endfunc sp_min_warm_entrypoint
229
230/*
231 * The function to restore the registers from SMC context and return
232 * to the mode restored to SPSR.
233 *
234 * Arguments : r0 must point to the SMC context to restore from.
235 */
236func sp_min_exit
Soby Mathewf3e3a432017-03-30 14:42:54 +0100237 monitor_exit
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100238endfunc sp_min_exit