Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <common/debug.h> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 10 | #include <cortex_a57.h> |
| 11 | #include <cpu_macros.S> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 12 | |
| 13 | /* --------------------------------------------- |
| 14 | * Disable intra-cluster coherency |
| 15 | * Clobbers: r0-r1 |
| 16 | * --------------------------------------------- |
| 17 | */ |
| 18 | func cortex_a57_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 19 | ldcopr16 r0, r1, CORTEX_A57_ECTLR |
| 20 | bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT |
| 21 | stcopr16 r0, r1, CORTEX_A57_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 22 | bx lr |
| 23 | endfunc cortex_a57_disable_smp |
| 24 | |
| 25 | /* --------------------------------------------- |
| 26 | * Disable all types of L2 prefetches. |
| 27 | * Clobbers: r0-r2 |
| 28 | * --------------------------------------------- |
| 29 | */ |
| 30 | func cortex_a57_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 31 | ldcopr16 r0, r1, CORTEX_A57_ECTLR |
| 32 | orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 33 | bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \ |
| 34 | CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK) |
| 35 | stcopr16 r0, r1, CORTEX_A57_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 36 | isb |
| 37 | dsb ish |
| 38 | bx lr |
| 39 | endfunc cortex_a57_disable_l2_prefetch |
| 40 | |
| 41 | /* --------------------------------------------- |
| 42 | * Disable debug interfaces |
| 43 | * --------------------------------------------- |
| 44 | */ |
| 45 | func cortex_a57_disable_ext_debug |
| 46 | mov r0, #1 |
| 47 | stcopr r0, DBGOSDLR |
| 48 | isb |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 49 | #if ERRATA_A57_817169 |
| 50 | /* |
| 51 | * Invalidate any TLB address |
| 52 | */ |
| 53 | mov r0, #0 |
| 54 | stcopr r0, TLBIMVA |
| 55 | #endif |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 56 | dsb sy |
| 57 | bx lr |
| 58 | endfunc cortex_a57_disable_ext_debug |
| 59 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 60 | /* -------------------------------------------------- |
| 61 | * Errata Workaround for Cortex A57 Errata #806969. |
| 62 | * This applies only to revision r0p0 of Cortex A57. |
| 63 | * Inputs: |
| 64 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 65 | * Shall clobber: r0-r3 |
| 66 | * -------------------------------------------------- |
| 67 | */ |
| 68 | func errata_a57_806969_wa |
| 69 | /* |
| 70 | * Compare r0 against revision r0p0 |
| 71 | */ |
| 72 | mov r2, lr |
| 73 | bl check_errata_806969 |
| 74 | mov lr, r2 |
| 75 | cmp r0, #ERRATA_NOT_APPLIES |
| 76 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 77 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 78 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA |
| 79 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 80 | 1: |
| 81 | bx lr |
| 82 | endfunc errata_a57_806969_wa |
| 83 | |
| 84 | func check_errata_806969 |
| 85 | mov r1, #0x00 |
| 86 | b cpu_rev_var_ls |
| 87 | endfunc check_errata_806969 |
| 88 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 89 | add_erratum_entry cortex_a57, ERRATUM(806969), ERRATA_A57_806969 |
| 90 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 91 | /* --------------------------------------------------- |
| 92 | * Errata Workaround for Cortex A57 Errata #813419. |
| 93 | * This applies only to revision r0p0 of Cortex A57. |
| 94 | * --------------------------------------------------- |
| 95 | */ |
| 96 | func check_errata_813419 |
| 97 | /* |
| 98 | * Even though this is only needed for revision r0p0, it |
| 99 | * is always applied due to limitations of the current |
| 100 | * errata framework. |
| 101 | */ |
| 102 | mov r0, #ERRATA_APPLIES |
| 103 | bx lr |
| 104 | endfunc check_errata_813419 |
| 105 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 106 | add_erratum_entry cortex_a57, ERRATUM(813419), ERRATA_A57_813419 |
| 107 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 108 | /* --------------------------------------------------- |
| 109 | * Errata Workaround for Cortex A57 Errata #813420. |
| 110 | * This applies only to revision r0p0 of Cortex A57. |
| 111 | * Inputs: |
| 112 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 113 | * Shall clobber: r0-r3 |
| 114 | * --------------------------------------------------- |
| 115 | */ |
| 116 | func errata_a57_813420_wa |
| 117 | /* |
| 118 | * Compare r0 against revision r0p0 |
| 119 | */ |
| 120 | mov r2, lr |
| 121 | bl check_errata_813420 |
| 122 | mov lr, r2 |
| 123 | cmp r0, #ERRATA_NOT_APPLIES |
| 124 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 125 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 126 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DCC_AS_DCCI |
| 127 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 128 | 1: |
| 129 | bx lr |
| 130 | endfunc errata_a57_813420_wa |
| 131 | |
| 132 | func check_errata_813420 |
| 133 | mov r1, #0x00 |
| 134 | b cpu_rev_var_ls |
| 135 | endfunc check_errata_813420 |
| 136 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 137 | add_erratum_entry cortex_a57, ERRATUM(813420), ERRATA_A57_813420 |
| 138 | |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 139 | /* --------------------------------------------------- |
| 140 | * Errata Workaround for Cortex A57 Errata #814670. |
| 141 | * This applies only to revision r0p0 of Cortex A57. |
| 142 | * Inputs: |
| 143 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 144 | * Shall clobber: r0-r3 |
| 145 | * --------------------------------------------------- |
| 146 | */ |
| 147 | func errata_a57_814670_wa |
| 148 | /* |
| 149 | * Compare r0 against revision r0p0 |
| 150 | */ |
| 151 | mov r2, lr |
| 152 | bl check_errata_814670 |
| 153 | cmp r0, #ERRATA_NOT_APPLIES |
| 154 | beq 1f |
| 155 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 156 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION |
| 157 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 158 | isb |
| 159 | 1: |
| 160 | bx r2 |
| 161 | endfunc errata_a57_814670_wa |
| 162 | |
| 163 | func check_errata_814670 |
| 164 | mov r1, #0x00 |
| 165 | b cpu_rev_var_ls |
| 166 | endfunc check_errata_814670 |
| 167 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 168 | add_erratum_entry cortex_a57, ERRATUM(814670), ERRATA_A57_814670 |
| 169 | |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 170 | /* ---------------------------------------------------- |
| 171 | * Errata Workaround for Cortex A57 Errata #817169. |
| 172 | * This applies only to revision <= r0p1 of Cortex A57. |
| 173 | * ---------------------------------------------------- |
| 174 | */ |
| 175 | func check_errata_817169 |
| 176 | /* |
| 177 | * Even though this is only needed for revision <= r0p1, it |
| 178 | * is always applied because of the low cost of the workaround. |
| 179 | */ |
| 180 | mov r0, #ERRATA_APPLIES |
| 181 | bx lr |
| 182 | endfunc check_errata_817169 |
| 183 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 184 | add_erratum_entry cortex_a57, ERRATUM(817169), ERRATA_A57_817169 |
| 185 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 186 | /* -------------------------------------------------------------------- |
| 187 | * Disable the over-read from the LDNP instruction. |
| 188 | * |
| 189 | * This applies to all revisions <= r1p2. The performance degradation |
| 190 | * observed with LDNP/STNP has been fixed on r1p3 and onwards. |
| 191 | * |
| 192 | * Inputs: |
| 193 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 194 | * Shall clobber: r0-r3 |
| 195 | * --------------------------------------------------------------------- |
| 196 | */ |
| 197 | func a57_disable_ldnp_overread |
| 198 | /* |
| 199 | * Compare r0 against revision r1p2 |
| 200 | */ |
| 201 | mov r2, lr |
| 202 | bl check_errata_disable_ldnp_overread |
| 203 | mov lr, r2 |
| 204 | cmp r0, #ERRATA_NOT_APPLIES |
| 205 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 206 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 207 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_OVERREAD |
| 208 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 209 | 1: |
| 210 | bx lr |
| 211 | endfunc a57_disable_ldnp_overread |
| 212 | |
| 213 | func check_errata_disable_ldnp_overread |
| 214 | mov r1, #0x12 |
| 215 | b cpu_rev_var_ls |
| 216 | endfunc check_errata_disable_ldnp_overread |
| 217 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 218 | add_erratum_entry cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT, disable_ldnp_overread |
| 219 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 220 | /* --------------------------------------------------- |
| 221 | * Errata Workaround for Cortex A57 Errata #826974. |
| 222 | * This applies only to revision <= r1p1 of Cortex A57. |
| 223 | * Inputs: |
| 224 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 225 | * Shall clobber: r0-r3 |
| 226 | * --------------------------------------------------- |
| 227 | */ |
| 228 | func errata_a57_826974_wa |
| 229 | /* |
| 230 | * Compare r0 against revision r1p1 |
| 231 | */ |
| 232 | mov r2, lr |
| 233 | bl check_errata_826974 |
| 234 | mov lr, r2 |
| 235 | cmp r0, #ERRATA_NOT_APPLIES |
| 236 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 237 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 238 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB |
| 239 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 240 | 1: |
| 241 | bx lr |
| 242 | endfunc errata_a57_826974_wa |
| 243 | |
| 244 | func check_errata_826974 |
| 245 | mov r1, #0x11 |
| 246 | b cpu_rev_var_ls |
| 247 | endfunc check_errata_826974 |
| 248 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 249 | add_erratum_entry cortex_a57, ERRATUM(826974), ERRATA_A57_826974 |
| 250 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 251 | /* --------------------------------------------------- |
| 252 | * Errata Workaround for Cortex A57 Errata #826977. |
| 253 | * This applies only to revision <= r1p1 of Cortex A57. |
| 254 | * Inputs: |
| 255 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 256 | * Shall clobber: r0-r3 |
| 257 | * --------------------------------------------------- |
| 258 | */ |
| 259 | func errata_a57_826977_wa |
| 260 | /* |
| 261 | * Compare r0 against revision r1p1 |
| 262 | */ |
| 263 | mov r2, lr |
| 264 | bl check_errata_826977 |
| 265 | mov lr, r2 |
| 266 | cmp r0, #ERRATA_NOT_APPLIES |
| 267 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 268 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 269 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE |
| 270 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 271 | 1: |
| 272 | bx lr |
| 273 | endfunc errata_a57_826977_wa |
| 274 | |
| 275 | func check_errata_826977 |
| 276 | mov r1, #0x11 |
| 277 | b cpu_rev_var_ls |
| 278 | endfunc check_errata_826977 |
| 279 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 280 | add_erratum_entry cortex_a57, ERRATUM(826977), ERRATA_A57_826977 |
| 281 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 282 | /* --------------------------------------------------- |
| 283 | * Errata Workaround for Cortex A57 Errata #828024. |
| 284 | * This applies only to revision <= r1p1 of Cortex A57. |
| 285 | * Inputs: |
| 286 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 287 | * Shall clobber: r0-r3 |
| 288 | * --------------------------------------------------- |
| 289 | */ |
| 290 | func errata_a57_828024_wa |
| 291 | /* |
| 292 | * Compare r0 against revision r1p1 |
| 293 | */ |
| 294 | mov r2, lr |
| 295 | bl check_errata_828024 |
| 296 | mov lr, r2 |
| 297 | cmp r0, #ERRATA_NOT_APPLIES |
| 298 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 299 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 300 | /* |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 301 | * Setting the relevant bits in CORTEX_A57_CPUACTLR has to be done in 2 |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 302 | * instructions here because the resulting bitmask doesn't fit in a |
| 303 | * 16-bit value so it cannot be encoded in a single instruction. |
| 304 | */ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 305 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA |
| 306 | orr64_imm r0, r1, (CORTEX_A57_CPUACTLR_DIS_L1_STREAMING | CORTEX_A57_CPUACTLR_DIS_STREAMING) |
| 307 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 308 | 1: |
| 309 | bx lr |
| 310 | endfunc errata_a57_828024_wa |
| 311 | |
| 312 | func check_errata_828024 |
| 313 | mov r1, #0x11 |
| 314 | b cpu_rev_var_ls |
| 315 | endfunc check_errata_828024 |
| 316 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 317 | add_erratum_entry cortex_a57, ERRATUM(828024), ERRATA_A57_828024 |
| 318 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 319 | /* --------------------------------------------------- |
| 320 | * Errata Workaround for Cortex A57 Errata #829520. |
| 321 | * This applies only to revision <= r1p2 of Cortex A57. |
| 322 | * Inputs: |
| 323 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 324 | * Shall clobber: r0-r3 |
| 325 | * --------------------------------------------------- |
| 326 | */ |
| 327 | func errata_a57_829520_wa |
| 328 | /* |
| 329 | * Compare r0 against revision r1p2 |
| 330 | */ |
| 331 | mov r2, lr |
| 332 | bl check_errata_829520 |
| 333 | mov lr, r2 |
| 334 | cmp r0, #ERRATA_NOT_APPLIES |
| 335 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 336 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 337 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR |
| 338 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 339 | 1: |
| 340 | bx lr |
| 341 | endfunc errata_a57_829520_wa |
| 342 | |
| 343 | func check_errata_829520 |
| 344 | mov r1, #0x12 |
| 345 | b cpu_rev_var_ls |
| 346 | endfunc check_errata_829520 |
| 347 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 348 | add_erratum_entry cortex_a57, ERRATUM(829520), ERRATA_A57_829520 |
| 349 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 350 | /* --------------------------------------------------- |
| 351 | * Errata Workaround for Cortex A57 Errata #833471. |
| 352 | * This applies only to revision <= r1p2 of Cortex A57. |
| 353 | * Inputs: |
| 354 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 355 | * Shall clobber: r0-r3 |
| 356 | * --------------------------------------------------- |
| 357 | */ |
| 358 | func errata_a57_833471_wa |
| 359 | /* |
| 360 | * Compare r0 against revision r1p2 |
| 361 | */ |
| 362 | mov r2, lr |
| 363 | bl check_errata_833471 |
| 364 | mov lr, r2 |
| 365 | cmp r0, #ERRATA_NOT_APPLIES |
| 366 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 367 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 368 | orr64_imm r1, r1, CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH |
| 369 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 370 | 1: |
| 371 | bx lr |
| 372 | endfunc errata_a57_833471_wa |
| 373 | |
| 374 | func check_errata_833471 |
| 375 | mov r1, #0x12 |
| 376 | b cpu_rev_var_ls |
| 377 | endfunc check_errata_833471 |
| 378 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 379 | add_erratum_entry cortex_a57, ERRATUM(833471), ERRATA_A57_833471 |
| 380 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 381 | /* --------------------------------------------------- |
| 382 | * Errata Workaround for Cortex A57 Errata #859972. |
| 383 | * This applies only to revision <= r1p3 of Cortex A57. |
| 384 | * Inputs: |
| 385 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 386 | * Shall clobber: r0-r3 |
| 387 | * --------------------------------------------------- |
| 388 | */ |
| 389 | func errata_a57_859972_wa |
| 390 | mov r2, lr |
| 391 | bl check_errata_859972 |
| 392 | mov lr, r2 |
| 393 | cmp r0, #ERRATA_NOT_APPLIES |
| 394 | beq 1f |
| 395 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 396 | orr64_imm r1, r1, CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH |
| 397 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 398 | 1: |
| 399 | bx lr |
| 400 | endfunc errata_a57_859972_wa |
| 401 | |
| 402 | func check_errata_859972 |
| 403 | mov r1, #0x13 |
| 404 | b cpu_rev_var_ls |
| 405 | endfunc check_errata_859972 |
| 406 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 407 | add_erratum_entry cortex_a57, ERRATUM(859972), ERRATA_A57_859972 |
| 408 | |
Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame] | 409 | func check_errata_cve_2017_5715 |
| 410 | mov r0, #ERRATA_MISSING |
| 411 | bx lr |
| 412 | endfunc check_errata_cve_2017_5715 |
| 413 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 414 | add_erratum_entry cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 |
| 415 | |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 416 | func check_errata_cve_2018_3639 |
| 417 | #if WORKAROUND_CVE_2018_3639 |
| 418 | mov r0, #ERRATA_APPLIES |
| 419 | #else |
| 420 | mov r0, #ERRATA_MISSING |
| 421 | #endif |
| 422 | bx lr |
| 423 | endfunc check_errata_cve_2018_3639 |
| 424 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 425 | add_erratum_entry cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
| 426 | |
John Powell | 7550aa2 | 2022-04-20 15:27:33 -0500 | [diff] [blame] | 427 | func check_errata_cve_2022_23960 |
| 428 | mov r0, #ERRATA_MISSING |
| 429 | bx lr |
| 430 | endfunc check_errata_cve_2022_23960 |
| 431 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 432 | add_erratum_entry cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 433 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 434 | /* ------------------------------------------------- |
| 435 | * The CPU Ops reset function for Cortex-A57. |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 436 | * Shall clobber: r0-r6 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 437 | * ------------------------------------------------- |
| 438 | */ |
| 439 | func cortex_a57_reset_func |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 440 | mov r5, lr |
| 441 | bl cpu_get_rev_var |
| 442 | mov r4, r0 |
| 443 | |
| 444 | #if ERRATA_A57_806969 |
| 445 | mov r0, r4 |
| 446 | bl errata_a57_806969_wa |
| 447 | #endif |
| 448 | |
| 449 | #if ERRATA_A57_813420 |
| 450 | mov r0, r4 |
| 451 | bl errata_a57_813420_wa |
| 452 | #endif |
| 453 | |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 454 | #if ERRATA_A57_814670 |
| 455 | mov r0, r4 |
| 456 | bl errata_a57_814670_wa |
| 457 | #endif |
| 458 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 459 | #if A57_DISABLE_NON_TEMPORAL_HINT |
| 460 | mov r0, r4 |
| 461 | bl a57_disable_ldnp_overread |
| 462 | #endif |
| 463 | |
| 464 | #if ERRATA_A57_826974 |
| 465 | mov r0, r4 |
| 466 | bl errata_a57_826974_wa |
| 467 | #endif |
| 468 | |
| 469 | #if ERRATA_A57_826977 |
| 470 | mov r0, r4 |
| 471 | bl errata_a57_826977_wa |
| 472 | #endif |
| 473 | |
| 474 | #if ERRATA_A57_828024 |
| 475 | mov r0, r4 |
| 476 | bl errata_a57_828024_wa |
| 477 | #endif |
| 478 | |
| 479 | #if ERRATA_A57_829520 |
| 480 | mov r0, r4 |
| 481 | bl errata_a57_829520_wa |
| 482 | #endif |
| 483 | |
| 484 | #if ERRATA_A57_833471 |
| 485 | mov r0, r4 |
| 486 | bl errata_a57_833471_wa |
| 487 | #endif |
| 488 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 489 | #if ERRATA_A57_859972 |
| 490 | mov r0, r4 |
| 491 | bl errata_a57_859972_wa |
| 492 | #endif |
| 493 | |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 494 | #if WORKAROUND_CVE_2018_3639 |
| 495 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 496 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE |
| 497 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 498 | isb |
| 499 | dsb sy |
| 500 | #endif |
| 501 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 502 | /* --------------------------------------------- |
| 503 | * Enable the SMP bit. |
| 504 | * --------------------------------------------- |
| 505 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 506 | ldcopr16 r0, r1, CORTEX_A57_ECTLR |
| 507 | orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT |
| 508 | stcopr16 r0, r1, CORTEX_A57_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 509 | isb |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 510 | bx r5 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 511 | endfunc cortex_a57_reset_func |
| 512 | |
| 513 | /* ---------------------------------------------------- |
| 514 | * The CPU Ops core power down function for Cortex-A57. |
| 515 | * ---------------------------------------------------- |
| 516 | */ |
| 517 | func cortex_a57_core_pwr_dwn |
| 518 | push {r12, lr} |
| 519 | |
| 520 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 521 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 522 | ldcopr r0, SCTLR |
| 523 | tst r0, #SCTLR_C_BIT |
| 524 | ASM_ASSERT(eq) |
| 525 | #endif |
| 526 | |
| 527 | /* --------------------------------------------- |
| 528 | * Disable the L2 prefetches. |
| 529 | * --------------------------------------------- |
| 530 | */ |
| 531 | bl cortex_a57_disable_l2_prefetch |
| 532 | |
| 533 | /* --------------------------------------------- |
| 534 | * Flush L1 caches. |
| 535 | * --------------------------------------------- |
| 536 | */ |
| 537 | mov r0, #DC_OP_CISW |
| 538 | bl dcsw_op_level1 |
| 539 | |
| 540 | /* --------------------------------------------- |
| 541 | * Come out of intra cluster coherency |
| 542 | * --------------------------------------------- |
| 543 | */ |
| 544 | bl cortex_a57_disable_smp |
| 545 | |
| 546 | /* --------------------------------------------- |
| 547 | * Force the debug interfaces to be quiescent |
| 548 | * --------------------------------------------- |
| 549 | */ |
| 550 | pop {r12, lr} |
| 551 | b cortex_a57_disable_ext_debug |
| 552 | endfunc cortex_a57_core_pwr_dwn |
| 553 | |
| 554 | /* ------------------------------------------------------- |
| 555 | * The CPU Ops cluster power down function for Cortex-A57. |
| 556 | * Clobbers: r0-r3 |
| 557 | * ------------------------------------------------------- |
| 558 | */ |
| 559 | func cortex_a57_cluster_pwr_dwn |
| 560 | push {r12, lr} |
| 561 | |
| 562 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 563 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 564 | ldcopr r0, SCTLR |
| 565 | tst r0, #SCTLR_C_BIT |
| 566 | ASM_ASSERT(eq) |
| 567 | #endif |
| 568 | |
| 569 | /* --------------------------------------------- |
| 570 | * Disable the L2 prefetches. |
| 571 | * --------------------------------------------- |
| 572 | */ |
| 573 | bl cortex_a57_disable_l2_prefetch |
| 574 | |
| 575 | /* --------------------------------------------- |
| 576 | * Flush L1 caches. |
| 577 | * --------------------------------------------- |
| 578 | */ |
| 579 | mov r0, #DC_OP_CISW |
| 580 | bl dcsw_op_level1 |
| 581 | |
| 582 | /* --------------------------------------------- |
| 583 | * Disable the optional ACP. |
| 584 | * --------------------------------------------- |
| 585 | */ |
| 586 | bl plat_disable_acp |
| 587 | |
| 588 | /* --------------------------------------------- |
| 589 | * Flush L2 caches. |
| 590 | * --------------------------------------------- |
| 591 | */ |
| 592 | mov r0, #DC_OP_CISW |
| 593 | bl dcsw_op_level2 |
| 594 | |
| 595 | /* --------------------------------------------- |
| 596 | * Come out of intra cluster coherency |
| 597 | * --------------------------------------------- |
| 598 | */ |
| 599 | bl cortex_a57_disable_smp |
| 600 | |
| 601 | /* --------------------------------------------- |
| 602 | * Force the debug interfaces to be quiescent |
| 603 | * --------------------------------------------- |
| 604 | */ |
| 605 | pop {r12, lr} |
| 606 | b cortex_a57_disable_ext_debug |
| 607 | endfunc cortex_a57_cluster_pwr_dwn |
| 608 | |
Boyan Karatotev | b1335b7 | 2023-01-26 17:30:09 +0000 | [diff] [blame] | 609 | errata_report_shim cortex_a57 |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 610 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 611 | declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ |
| 612 | cortex_a57_reset_func, \ |
| 613 | cortex_a57_core_pwr_dwn, \ |
| 614 | cortex_a57_cluster_pwr_dwn |