| developer | 8d3be08 | 2022-11-03 19:49:23 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PTP3_PLAT_H |
| 8 | #define PTP3_PLAT_H |
| 9 | |
| 10 | #include <lib/mmio.h> |
| 11 | #include <lib/utils_def.h> |
| 12 | #include <ptp3_common.h> |
| 13 | |
| 14 | /* CPU info */ |
| 15 | #define NR_PTP3_CFG_CPU U(8) |
| 16 | #define PTP3_CFG_CPU_START_ID_L U(0) |
| 17 | #define PTP3_CFG_CPU_START_ID_B U(4) |
| 18 | #define PTP3_CFG_CPU_END_ID U(7) |
| 19 | |
| 20 | #define NR_PTP3_CFG1_DATA U(2) |
| 21 | #define PTP3_CFG1_MASK 0x3000 |
| 22 | |
| 23 | #define NR_PTP3_CFG2_DATA U(5) |
| 24 | |
| 25 | #define PTP3_CFG3_MASK1 0x1180 |
| 26 | #define PTP3_CFG3_MASK2 0x35C0 |
| 27 | #define PTP3_CFG3_MASK3 0x3DC0 |
| 28 | |
| 29 | /* Central control */ |
| 30 | static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = { |
| 31 | {0x0C53A2A0, 0x1000}, |
| 32 | {0x0C53A2A4, 0x1000} |
| 33 | }; |
| 34 | |
| 35 | static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = { |
| 36 | {0x0C530404, 0x3A1000}, |
| 37 | {0x0C530428, 0x13E0408}, |
| 38 | {0x0C530434, 0xB22800}, |
| 39 | {0x0C53043C, 0x750}, |
| 40 | {0x0C530440, 0x0222c4cc} |
| 41 | }; |
| 42 | |
| 43 | static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0x2D80}; |
| 44 | static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00}; |
| 45 | |
| 46 | #endif /* PTP3_PLAT_H */ |