| Pankaj Gupta | 87d388e | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2018-2020 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef NXP_SMMU_H |
| 9 | #define NXP_SMMU_H |
| 10 | |
| 11 | #define SMMU_SCR0 (0x0) |
| 12 | #define SMMU_NSCR0 (0x400) |
| Howard Lu | b41f1ed | 2022-11-01 19:45:46 +0800 | [diff] [blame] | 13 | #define SMMU_SACR (0x10) |
| Pankaj Gupta | 87d388e | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 14 | |
| 15 | #define SCR0_CLIENTPD_MASK 0x00000001 |
| 16 | #define SCR0_USFCFG_MASK 0x00000400 |
| 17 | |
| Howard Lu | b41f1ed | 2022-11-01 19:45:46 +0800 | [diff] [blame] | 18 | #define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U) |
| 19 | |
| Pankaj Gupta | 87d388e | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 20 | static inline void bypass_smmu(uintptr_t smmu_base_addr) |
| 21 | { |
| 22 | uint32_t val; |
| 23 | |
| 24 | val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) & |
| 25 | ~(SCR0_USFCFG_MASK); |
| 26 | mmio_write_32((smmu_base_addr + SMMU_SCR0), val); |
| 27 | |
| 28 | val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & |
| 29 | ~(SCR0_USFCFG_MASK); |
| 30 | mmio_write_32((smmu_base_addr + SMMU_NSCR0), val); |
| 31 | } |
| 32 | |
| Howard Lu | b41f1ed | 2022-11-01 19:45:46 +0800 | [diff] [blame] | 33 | static inline void smmu_cache_unlock(uintptr_t smmu_base_addr) |
| 34 | { |
| 35 | uint32_t val; |
| 36 | |
| 37 | val = mmio_read_32((smmu_base_addr + SMMU_SACR)); |
| 38 | val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT; |
| 39 | mmio_write_32((smmu_base_addr + SMMU_SACR), val); |
| 40 | } |
| 41 | |
| Pankaj Gupta | 87d388e | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 42 | #endif |