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Pankaj Gupta74f7b142020-12-09 14:02:38 +05301/*
Biwen Lied6dc9b2021-01-05 14:58:57 +08002 * Copyright 2018-2022 NXP
Pankaj Gupta74f7b142020-12-09 14:02:38 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#ifndef DCFG_H
9#define DCFG_H
10
11#include <endian.h>
12
13#if defined(CONFIG_CHASSIS_2)
14#include <dcfg_lsch2.h>
Biwen Lied6dc9b2021-01-05 14:58:57 +080015#elif defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3)
Pankaj Gupta74f7b142020-12-09 14:02:38 +053016#include <dcfg_lsch3.h>
17#endif
18
19#ifdef NXP_GUR_BE
20#define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
21#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
22#elif defined(NXP_GUR_LE)
23#define gur_in32(a) mmio_read_32((uintptr_t)(a))
24#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v)
25#else
26#error Please define CCSR GUR register endianness
27#endif
28
29typedef struct {
Jiafei Panb27ac802021-07-20 17:14:32 +080030 union {
31 uint32_t val;
32 struct {
33 uint32_t min_ver:4;
34 uint32_t maj_ver:4;
35#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
36 uint32_t personality:6;
37 uint32_t rsv1:2;
38#elif defined(CONFIG_CHASSIS_2)
39 uint32_t personality:8;
40
Pankaj Gupta74f7b142020-12-09 14:02:38 +053041#endif
Jiafei Panb27ac802021-07-20 17:14:32 +080042#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
43 uint32_t dev_id:6;
44 uint32_t rsv2:2;
45 uint32_t family:4;
46#elif defined(CONFIG_CHASSIS_2)
47 uint32_t dev_id:12;
48#endif
49 uint32_t mfr_id;
50 } __packed bf;
51 struct {
52 uint32_t maj_min:8;
53 uint32_t version; /* SoC version without major and minor info */
54 } __packed bf_ver;
55 } __packed svr_reg;
Pankaj Gupta74f7b142020-12-09 14:02:38 +053056 bool sec_enabled;
Jiafei Panb27ac802021-07-20 17:14:32 +080057 bool is_populated;
Pankaj Gupta74f7b142020-12-09 14:02:38 +053058} soc_info_t;
59
60typedef struct {
61 bool is_populated;
62 uint8_t ocram_present;
63 uint8_t ddrc1_present;
Jiafei Panb27ac802021-07-20 17:14:32 +080064#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
Pankaj Gupta74f7b142020-12-09 14:02:38 +053065 uint8_t ddrc2_present;
66#endif
67} devdisr5_info_t;
68
69typedef struct {
70 uint32_t porsr1;
71 uintptr_t g_nxp_dcfg_addr;
72 unsigned long nxp_sysclk_freq;
73 unsigned long nxp_ddrclk_freq;
74 unsigned int nxp_plat_clk_divider;
75} dcfg_init_info_t;
76
77
78struct sysinfo {
79 unsigned long freq_platform;
80 unsigned long freq_ddr_pll0;
81 unsigned long freq_ddr_pll1;
82};
83
84int get_clocks(struct sysinfo *sys);
85
86/* Read the PORSR1 register */
87uint32_t read_reg_porsr1(void);
88
89/*******************************************************************************
90 * Returns true if secur eboot is enabled on board
91 * mode = 0 (development mode - sb_en = 1)
92 * mode = 1 (production mode - ITS = 1)
93 ******************************************************************************/
94bool check_boot_mode_secure(uint32_t *mode);
95
Elyes Haouasd94f9432023-02-13 10:38:45 +010096const soc_info_t *get_soc_info(void);
97const devdisr5_info_t *get_devdisr5_info(void);
Pankaj Gupta74f7b142020-12-09 14:02:38 +053098
99void dcfg_init(dcfg_init_info_t *dcfg_init_data);
100bool is_sec_enabled(void);
101
102void error_handler(int error_code);
103#endif /* DCFG_H */