blob: dc3d71dd45aa16b3fc4143fb146fd907f83d47d6 [file] [log] [blame]
Nariman Poushinc703f902018-03-07 10:29:57 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <bl_common.h>
8#include <debug.h>
9#include <plat_arm.h>
10#include <sgm_plat_config.h>
11#include <soc_css.h>
12
13void bl1_early_platform_setup(void)
14{
Nariman Poushinc703f902018-03-07 10:29:57 +000015
Girish Pathak66dd23c2018-10-02 15:18:34 +010016 /* Initialize the console before anything else */
Nariman Poushinc703f902018-03-07 10:29:57 +000017 arm_bl1_early_platform_setup();
18
Girish Pathak66dd23c2018-10-02 15:18:34 +010019 /* Initialize the platform configuration structure */
20 plat_config_init();
21
Nariman Poushinc703f902018-03-07 10:29:57 +000022#if !HW_ASSISTED_COHERENCY
23 /*
24 * Initialize Interconnect for this cluster during cold boot.
25 * No need for locks as no other CPU is active.
26 */
27 plat_arm_interconnect_init();
28 /*
29 * Enable Interconnect coherency for the primary CPU's cluster.
30 */
31 plat_arm_interconnect_enter_coherency();
32#endif
33}