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Vikram Kanigiri510d87b2016-01-29 12:32:58 +00001/*
Summer Qin5ce394c2018-03-12 11:28:26 +08002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00005 */
6
7#include <arm_def.h>
8#include <assert.h>
9#include <debug.h>
Nariman Poushin8b8df932018-04-27 18:49:52 +010010#include <plat_arm.h>
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000011#include <platform_def.h>
12#include <tzc_dmc500.h>
13
14/*******************************************************************************
15 * Initialize the DMC500-TrustZone Controller for ARM standard platforms.
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000016 * When booting an EL3 payload, this is simplified: we configure region 0 with
17 * secure access only and do not enable any other region.
18 ******************************************************************************/
Summer Qin5ce394c2018-03-12 11:28:26 +080019void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data,
20 const arm_tzc_regions_info_t *tzc_regions)
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000021{
Summer Qin5ce394c2018-03-12 11:28:26 +080022#ifndef EL3_PAYLOAD_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010023 unsigned int region_index = 1U;
Summer Qin5ce394c2018-03-12 11:28:26 +080024 const arm_tzc_regions_info_t *p;
25 const arm_tzc_regions_info_t init_tzc_regions[] = {
26 ARM_TZC_REGIONS_DEF,
27 {0}
28 };
29#endif
30
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000031 assert(plat_driver_data);
32
33 INFO("Configuring DMC-500 TZ Settings\n");
34
35 tzc_dmc500_driver_init(plat_driver_data);
36
37#ifndef EL3_PAYLOAD_BASE
Summer Qin5ce394c2018-03-12 11:28:26 +080038 if (tzc_regions == NULL)
39 p = init_tzc_regions;
40 else
41 p = tzc_regions;
42
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000043 /* Region 0 set to no access by default */
44 tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0);
45
Summer Qin5ce394c2018-03-12 11:28:26 +080046 /* Rest Regions set according to tzc_regions array */
47 for (; p->base != 0ULL; p++) {
48 tzc_dmc500_configure_region(region_index, p->base, p->end,
49 p->sec_attr, p->nsaid_permissions);
50 region_index++;
51 }
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000052
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010053 INFO("Total %u regions set.\n", region_index);
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000054
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000055#else
56 /* Allow secure access only to DRAM for EL3 payloads */
57 tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0);
58#endif
59 /*
60 * Raise an exception if a NS device tries to access secure memory
61 * TODO: Add interrupt handling support.
62 */
63 tzc_dmc500_set_action(TZC_ACTION_RV_LOWERR);
64
65 /*
66 * Flush the configuration settings to have an affect. Validate
67 * flush by checking FILTER_EN is set on region 1 attributes
68 * register.
69 */
70 tzc_dmc500_config_complete();
71
72 /*
73 * Wait for the flush to complete.
74 * TODO: Have a timeout for this loop
75 */
76 while (tzc_dmc500_verify_complete())
77 ;
78}