David Pu | 70f6597 | 2019-03-18 15:14:49 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef TEGRA194_RAS_PRIVATE |
| 8 | #define TEGRA194_RAS_PRIVATE |
| 9 | |
| 10 | #include <stdint.h> |
| 11 | |
| 12 | /* Implementation defined RAS error and corresponding error message */ |
| 13 | struct ras_error { |
| 14 | const char *error_msg; |
| 15 | /* IERR(bits[15:8]) from ERR<n>STATUS */ |
| 16 | uint8_t error_code; |
| 17 | }; |
| 18 | |
| 19 | /* RAS error node-specific auxiliary data */ |
| 20 | struct ras_aux_data { |
David Pu | c14ae53 | 2019-05-16 17:20:27 -0700 | [diff] [blame] | 21 | /* name for current RAS node. */ |
| 22 | const char *name; |
David Pu | 70f6597 | 2019-03-18 15:14:49 -0700 | [diff] [blame] | 23 | /* point to null-terminated ras_error array to convert error code to msg. */ |
| 24 | const struct ras_error *error_records; |
| 25 | /* |
| 26 | * function to return an value which needs to be programmed into ERXCTLR_EL1 |
| 27 | * to enable all specified RAS errors for current node. |
| 28 | */ |
| 29 | uint64_t (*err_ctrl)(void); |
| 30 | }; |
| 31 | |
| 32 | /* IFU Uncorrectable RAS ERROR */ |
| 33 | #define IFU_UNCORR_RAS_ERROR_LIST(X) |
| 34 | |
| 35 | /* JSR_RET Uncorrectable RAS ERROR */ |
| 36 | #define JSR_RET_UNCORR_RAS_ERROR_LIST(X) \ |
| 37 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 38 | X(JSR_RET, 35, 0x13, "Floating Point Register File Parity Error") \ |
| 39 | X(JSR_RET, 34, 0x12, "Integer Register File Parity Error") \ |
| 40 | X(JSR_RET, 33, 0x11, "Garbage Bundle") \ |
| 41 | X(JSR_RET, 32, 0x10, "Bundle Completion Timeout") |
| 42 | |
| 43 | /* JSR_MTS Uncorrectable RAS ERROR */ |
| 44 | #define JSR_MTS_UNCORR_RAS_ERROR_LIST(X) \ |
| 45 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 46 | X(JSR_MTS, 40, 0x28, "CoreSight Access Error") \ |
| 47 | X(JSR_MTS, 39, 0x27, "Dual Execution Uncorrectable Error") \ |
| 48 | X(JSR_MTS, 37, 0x25, "CTU MMIO Region") \ |
| 49 | X(JSR_MTS, 36, 0x24, "MTS MMCRAB Region Access") \ |
| 50 | X(JSR_MTS, 35, 0x23, "MTS_CARVEOUT Access from ARM SW") \ |
| 51 | X(JSR_MTS, 34, 0x22, "NAFLL PLL Failure to Lock") \ |
| 52 | X(JSR_MTS, 32, 0x20, "Internal Uncorrectable MTS Error") |
| 53 | |
| 54 | /* LSD_STQ Uncorrectable RAS ERROR */ |
| 55 | #define LSD_STQ_UNCORR_RAS_ERROR_LIST(X) \ |
| 56 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 57 | X(LSD_STQ, 41, 0x39, "Coherent Cache Data Store Multi-Line ECC Error") \ |
| 58 | X(LSD_STQ, 40, 0x38, "Coherent Cache Data Store Uncorrectable ECC Error") \ |
| 59 | X(LSD_STQ, 38, 0x36, "Coherent Cache Data Load Uncorrectable ECC Error") \ |
| 60 | X(LSD_STQ, 33, 0x31, "Coherent Cache Tag Store Parity Error") \ |
| 61 | X(LSD_STQ, 32, 0x30, "Coherent Cache Tag Load Parity Error") |
| 62 | |
| 63 | /* LSD_DCC Uncorrectable RAS ERROR */ |
| 64 | #define LSD_DCC_UNCORR_RAS_ERROR_LIST(X) \ |
| 65 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 66 | X(LSD_DCC, 41, 0x49, "BTU Copy Mini-Cache PPN Multi-Hit Error") \ |
| 67 | X(LSD_DCC, 39, 0x47, "Coherent Cache Data Uncorrectable ECC Error") \ |
| 68 | X(LSD_DCC, 37, 0x45, "Version Cache Byte-Enable Parity Error") \ |
| 69 | X(LSD_DCC, 36, 0x44, "Version Cache Data Uncorrectable ECC Error") \ |
| 70 | X(LSD_DCC, 33, 0x41, "BTU Copy Coherent Cache PPN Parity Error") \ |
| 71 | X(LSD_DCC, 32, 0x40, "BTU Copy Coherent Cache VPN Parity Error") |
| 72 | |
| 73 | /* LSD_L1HPF Uncorrectable RAS ERROR */ |
| 74 | #define LSD_L1HPF_UNCORR_RAS_ERROR_LIST(X) |
| 75 | |
| 76 | /* L2 Uncorrectable RAS ERROR */ |
| 77 | #define L2_UNCORR_RAS_ERROR_LIST(X) \ |
| 78 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 79 | X(L2, 56, 0x68, "URT Timeout") \ |
| 80 | X(L2, 55, 0x67, "L2 Protocol Violation") \ |
| 81 | X(L2, 54, 0x66, "SCF to L2 Slave Error Read") \ |
| 82 | X(L2, 53, 0x65, "SCF to L2 Slave Error Write") \ |
| 83 | X(L2, 52, 0x64, "SCF to L2 Decode Error Read") \ |
| 84 | X(L2, 51, 0x63, "SCF to L2 Decode Error Write") \ |
| 85 | X(L2, 50, 0x62, "SCF to L2 Request Response Interface Parity Errors") \ |
| 86 | X(L2, 49, 0x61, "SCF to L2 Advance notice interface parity errors") \ |
| 87 | X(L2, 48, 0x60, "SCF to L2 Filldata Parity Errors") \ |
| 88 | X(L2, 47, 0x5F, "SCF to L2 UnCorrectable ECC Data Error on interface") \ |
| 89 | X(L2, 45, 0x5D, "Core 1 to L2 Parity Error") \ |
| 90 | X(L2, 44, 0x5C, "Core 0 to L2 Parity Error") \ |
| 91 | X(L2, 43, 0x5B, "L2 Multi-Hit") \ |
| 92 | X(L2, 42, 0x5A, "L2 URT Tag Parity Error") \ |
| 93 | X(L2, 41, 0x59, "L2 NTT Tag Parity Error") \ |
| 94 | X(L2, 40, 0x58, "L2 MLT Tag Parity Error") \ |
| 95 | X(L2, 39, 0x57, "L2 URD Data") \ |
| 96 | X(L2, 38, 0x56, "L2 NTP Data") \ |
| 97 | X(L2, 36, 0x54, "L2 MLC Uncorrectable Clean") \ |
| 98 | X(L2, 35, 0x53, "L2 URD Uncorrectable Dirty") \ |
| 99 | X(L2, 34, 0x52, "L2 MLC Uncorrectable Dirty") |
| 100 | |
| 101 | /* CLUSTER_CLOCKS Uncorrectable RAS ERROR */ |
| 102 | #define CLUSTER_CLOCKS_UNCORR_RAS_ERROR_LIST(X) \ |
| 103 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 104 | X(CLUSTER_CLOCKS, 32, 0xE4, "Frequency Monitor Error") |
| 105 | |
| 106 | /* MMU Uncorrectable RAS ERROR */ |
| 107 | #define MMU_UNCORR_RAS_ERROR_LIST(X) |
| 108 | |
| 109 | /* L3 Uncorrectable RAS ERROR */ |
| 110 | #define L3_UNCORR_RAS_ERROR_LIST(X) \ |
| 111 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 112 | X(L3, 43, 0x7B, "SNOC Interface Parity Error") \ |
| 113 | X(L3, 42, 0x7A, "MCF Interface Parity Error") \ |
| 114 | X(L3, 41, 0x79, "L3 Tag Parity Error") \ |
| 115 | X(L3, 40, 0x78, "L3 Dir Parity Error") \ |
| 116 | X(L3, 39, 0x77, "L3 Uncorrectable ECC Error") \ |
| 117 | X(L3, 37, 0x75, "Multi-Hit CAM Error") \ |
| 118 | X(L3, 36, 0x74, "Multi-Hit Tag Error") \ |
| 119 | X(L3, 35, 0x73, "Unrecognized Command Error") \ |
| 120 | X(L3, 34, 0x72, "L3 Protocol Error") |
| 121 | |
| 122 | /* CCPMU Uncorrectable RAS ERROR */ |
| 123 | #define CCPMU_UNCORR_RAS_ERROR_LIST(X) \ |
| 124 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 125 | X(CCPMU, 40, 0x87, "CoreSight Access Error") \ |
| 126 | X(CCPMU, 36, 0x84, "MCE Ucode Error") \ |
| 127 | X(CCPMU, 35, 0x83, "MCE IL1 Parity Error") \ |
| 128 | X(CCPMU, 34, 0x82, "MCE Timeout Error") \ |
| 129 | X(CCPMU, 33, 0x81, "CRAB Access Error") \ |
| 130 | X(CCPMU, 32, 0x80, "MCE Memory Access Error") |
| 131 | |
| 132 | /* SCF_IOB Uncorrectable RAS ERROR */ |
| 133 | #define SCF_IOB_UNCORR_RAS_ERROR_LIST(X) \ |
| 134 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 135 | X(SCF_IOB, 41, 0x99, "Request parity error") \ |
| 136 | X(SCF_IOB, 40, 0x98, "Putdata parity error") \ |
| 137 | X(SCF_IOB, 39, 0x97, "Uncorrectable ECC on Putdata") \ |
| 138 | X(SCF_IOB, 38, 0x96, "CBB Interface Error") \ |
| 139 | X(SCF_IOB, 37, 0x95, "MMCRAB Error") \ |
| 140 | X(SCF_IOB, 36, 0x94, "IHI Interface Error") \ |
| 141 | X(SCF_IOB, 35, 0x93, "CRI Error") \ |
| 142 | X(SCF_IOB, 34, 0x92, "TBX Interface Error") \ |
| 143 | X(SCF_IOB, 33, 0x91, "EVP Interface Error") |
| 144 | |
| 145 | /* SCF_SNOC Uncorrectable RAS ERROR */ |
| 146 | #define SCF_SNOC_UNCORR_RAS_ERROR_LIST(X) \ |
| 147 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 148 | X(SCF_SNOC, 42, 0xAA, "Misc Client Parity Error") \ |
| 149 | X(SCF_SNOC, 41, 0xA9, "Misc Filldata Parity Error") \ |
| 150 | X(SCF_SNOC, 40, 0xA8, "Uncorrectable ECC Misc Client") \ |
| 151 | X(SCF_SNOC, 39, 0xA7, "DVMU Interface Parity Error") \ |
| 152 | X(SCF_SNOC, 38, 0xA6, "DVMU Interface Timeout Error") \ |
| 153 | X(SCF_SNOC, 37, 0xA5, "CPE Request Error") \ |
| 154 | X(SCF_SNOC, 36, 0xA4, "CPE Response Error") \ |
| 155 | X(SCF_SNOC, 35, 0xA3, "CPE Timeout Error") \ |
| 156 | X(SCF_SNOC, 34, 0xA2, "Uncorrectable Carveout Error") |
| 157 | |
| 158 | /* SCF_CTU Uncorrectable RAS ERROR */ |
| 159 | #define SCF_CTU_UNCORR_RAS_ERROR_LIST(X) \ |
| 160 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 161 | X(SCF_CTU, 39, 0xB7, "Timeout error for TRC_DMA request") \ |
| 162 | X(SCF_CTU, 38, 0xB6, "Timeout error for CTU Snp") \ |
| 163 | X(SCF_CTU, 37, 0xB5, "Parity error in CTU TAG RAM") \ |
| 164 | X(SCF_CTU, 36, 0xB3, "Parity error in CTU DATA RAM") \ |
| 165 | X(SCF_CTU, 35, 0xB4, "Parity error for Cluster Rsp") \ |
| 166 | X(SCF_CTU, 34, 0xB2, "Parity error for TRL requests from 9 agents") \ |
| 167 | X(SCF_CTU, 33, 0xB1, "Parity error for MCF request") \ |
| 168 | X(SCF_CTU, 32, 0xB0, "TRC DMA fillsnoop parity error") |
| 169 | |
| 170 | /* CMU_CLOCKS Uncorrectable RAS ERROR */ |
| 171 | #define CMU_CLOCKS_UNCORR_RAS_ERROR_LIST(X) \ |
| 172 | /* Name, ERR_CTRL, IERR, ISA Desc */ \ |
| 173 | X(CMU_CLOCKS, 39, 0xC7, "Cluster 3 frequency monitor error") \ |
| 174 | X(CMU_CLOCKS, 38, 0xC6, "Cluster 2 frequency monitor error") \ |
| 175 | X(CMU_CLOCKS, 37, 0xC5, "Cluster 1 frequency monitor error") \ |
| 176 | X(CMU_CLOCKS, 36, 0xC3, "Cluster 0 frequency monitor error") \ |
| 177 | X(CMU_CLOCKS, 35, 0xC4, "Voltage error on ADC1 Monitored Logic") \ |
| 178 | X(CMU_CLOCKS, 34, 0xC2, "Voltage error on ADC0 Monitored Logic") \ |
| 179 | X(CMU_CLOCKS, 33, 0xC1, "Lookup Table 1 Parity Error") \ |
| 180 | X(CMU_CLOCKS, 32, 0xC0, "Lookup Table 0 Parity Error") |
| 181 | |
| 182 | /* |
| 183 | * Define one ras_error entry. |
| 184 | * |
| 185 | * This macro wille be used to to generate ras_error records for each node |
| 186 | * defined by <NODE_NAME>_UNCORR_RAS_ERROR_LIST macro. |
| 187 | */ |
| 188 | #define DEFINE_ONE_RAS_ERROR_MSG(unit, ras_bit, ierr, msg) \ |
| 189 | { \ |
| 190 | .error_msg = (msg), \ |
| 191 | .error_code = (ierr) \ |
| 192 | }, |
| 193 | |
| 194 | /* |
| 195 | * Set one implementation defined bit in ERR<n>CTLR |
| 196 | * |
| 197 | * This macro will be used to collect all defined ERR_CTRL bits for each node |
| 198 | * defined by <NODE_NAME>_UNCORR_RAS_ERROR_LIST macro. |
| 199 | */ |
| 200 | #define DEFINE_ENABLE_RAS_BIT(unit, ras_bit, ierr, msg) \ |
| 201 | do { \ |
| 202 | val |= (1ULL << ras_bit##U); \ |
| 203 | } while (0); |
| 204 | |
| 205 | /* Represent one RAS node with 0 or more error bits (ERR_CTLR) enabled */ |
| 206 | #define DEFINE_ONE_RAS_NODE(node) \ |
| 207 | static const struct ras_error node##_uncorr_ras_errors[] = { \ |
| 208 | node##_UNCORR_RAS_ERROR_LIST(DEFINE_ONE_RAS_ERROR_MSG) \ |
| 209 | { \ |
| 210 | NULL, \ |
| 211 | 0U \ |
| 212 | }, \ |
| 213 | }; \ |
| 214 | static inline uint64_t node##_err_ctrl(void) \ |
| 215 | { \ |
| 216 | uint64_t val = 0ULL; \ |
| 217 | node##_UNCORR_RAS_ERROR_LIST(DEFINE_ENABLE_RAS_BIT) \ |
| 218 | return val; \ |
| 219 | } |
| 220 | |
| 221 | #define DEFINE_ONE_RAS_AUX_DATA(node) \ |
| 222 | { \ |
David Pu | c14ae53 | 2019-05-16 17:20:27 -0700 | [diff] [blame] | 223 | .name = #node, \ |
David Pu | 70f6597 | 2019-03-18 15:14:49 -0700 | [diff] [blame] | 224 | .error_records = node##_uncorr_ras_errors, \ |
| 225 | .err_ctrl = &node##_err_ctrl \ |
| 226 | }, |
| 227 | |
| 228 | #define PER_CORE_RAS_NODE_LIST(X) \ |
| 229 | X(IFU) \ |
| 230 | X(JSR_RET) \ |
| 231 | X(JSR_MTS) \ |
| 232 | X(LSD_STQ) \ |
| 233 | X(LSD_DCC) \ |
| 234 | X(LSD_L1HPF) |
| 235 | |
| 236 | #define PER_CORE_RAS_GROUP_NODES PER_CORE_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) |
| 237 | |
| 238 | #define PER_CLUSTER_RAS_NODE_LIST(X) \ |
| 239 | X(L2) \ |
| 240 | X(CLUSTER_CLOCKS) \ |
| 241 | X(MMU) |
| 242 | |
| 243 | #define PER_CLUSTER_RAS_GROUP_NODES PER_CLUSTER_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) |
| 244 | |
| 245 | #define SCF_L3_BANK_RAS_NODE_LIST(X) X(L3) |
| 246 | |
| 247 | /* we have 4 SCF_L3 nodes:3*256 + L3_Bank_ID(0-3) */ |
| 248 | #define SCF_L3_BANK_RAS_GROUP_NODES \ |
| 249 | SCF_L3_BANK_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) \ |
| 250 | SCF_L3_BANK_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) \ |
| 251 | SCF_L3_BANK_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) \ |
| 252 | SCF_L3_BANK_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) |
| 253 | |
| 254 | #define CCPLEX_RAS_NODE_LIST(X) \ |
| 255 | X(CCPMU) \ |
| 256 | X(SCF_IOB) \ |
| 257 | X(SCF_SNOC) \ |
| 258 | X(SCF_CTU) \ |
| 259 | X(CMU_CLOCKS) |
| 260 | |
| 261 | #define CCPLEX_RAS_GROUP_NODES CCPLEX_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) |
| 262 | |
| 263 | #endif /* TEGRA194_RAS_PRIVATE */ |