Jay Buddhabhatti | 5b9f391 | 2023-02-02 22:34:03 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | /* ZynqMP power management enums and defines */ |
| 9 | |
| 10 | #ifndef ZYNQMP_PM_DEFS_H |
| 11 | #define ZYNQMP_PM_DEFS_H |
| 12 | |
| 13 | /********************************************************************* |
| 14 | * Macro definitions |
| 15 | ********************************************************************/ |
| 16 | |
| 17 | /* |
| 18 | * Version number is a 32bit value, like: |
| 19 | * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR |
| 20 | */ |
| 21 | #define PM_VERSION_MAJOR 1U |
| 22 | #define PM_VERSION_MINOR 1U |
| 23 | |
| 24 | #define PM_VERSION ((PM_VERSION_MAJOR << 16U) | PM_VERSION_MINOR) |
| 25 | |
| 26 | /** |
| 27 | * PM API versions |
| 28 | */ |
| 29 | /* Expected version of firmware APIs */ |
| 30 | #define FW_API_BASE_VERSION (1U) |
| 31 | /* Expected version of firmware API for feature check */ |
| 32 | #define FW_API_VERSION_2 (2U) |
| 33 | /* Version of APIs implemented in ATF */ |
| 34 | #define ATF_API_BASE_VERSION (1U) |
| 35 | /* Updating the QUERY_DATA API versioning as the bitmask functionality |
| 36 | * support is added in the v2.*/ |
| 37 | #define TFA_API_QUERY_DATA_VERSION (2U) |
| 38 | |
| 39 | /* Capabilities for RAM */ |
| 40 | #define PM_CAP_ACCESS 0x1U |
| 41 | #define PM_CAP_CONTEXT 0x2U |
| 42 | |
| 43 | /* APU processor states */ |
| 44 | #define PM_PROC_STATE_FORCEDOFF 0U |
| 45 | #define PM_PROC_STATE_ACTIVE 1U |
| 46 | #define PM_PROC_STATE_SLEEP 2U |
| 47 | #define PM_PROC_STATE_SUSPENDING 3U |
| 48 | |
| 49 | #define PM_SET_SUSPEND_MODE 0xa02 |
| 50 | |
| 51 | /********************************************************************* |
| 52 | * Enum definitions |
| 53 | ********************************************************************/ |
| 54 | |
| 55 | enum pm_node_id { |
| 56 | NODE_UNKNOWN = 0, |
| 57 | NODE_APU, |
| 58 | NODE_APU_0, |
| 59 | NODE_APU_1, |
| 60 | NODE_APU_2, |
| 61 | NODE_APU_3, |
| 62 | NODE_RPU, |
| 63 | NODE_RPU_0, |
| 64 | NODE_RPU_1, |
| 65 | NODE_PLD, |
| 66 | NODE_FPD, |
| 67 | NODE_OCM_BANK_0, |
| 68 | NODE_OCM_BANK_1, |
| 69 | NODE_OCM_BANK_2, |
| 70 | NODE_OCM_BANK_3, |
| 71 | NODE_TCM_0_A, |
| 72 | NODE_TCM_0_B, |
| 73 | NODE_TCM_1_A, |
| 74 | NODE_TCM_1_B, |
| 75 | NODE_L2, |
| 76 | NODE_GPU_PP_0, |
| 77 | NODE_GPU_PP_1, |
| 78 | NODE_USB_0, |
| 79 | NODE_USB_1, |
| 80 | NODE_TTC_0, |
| 81 | NODE_TTC_1, |
| 82 | NODE_TTC_2, |
| 83 | NODE_TTC_3, |
| 84 | NODE_SATA, |
| 85 | NODE_ETH_0, |
| 86 | NODE_ETH_1, |
| 87 | NODE_ETH_2, |
| 88 | NODE_ETH_3, |
| 89 | NODE_UART_0, |
| 90 | NODE_UART_1, |
| 91 | NODE_SPI_0, |
| 92 | NODE_SPI_1, |
| 93 | NODE_I2C_0, |
| 94 | NODE_I2C_1, |
| 95 | NODE_SD_0, |
| 96 | NODE_SD_1, |
| 97 | NODE_DP, |
| 98 | NODE_GDMA, |
| 99 | NODE_ADMA, |
| 100 | NODE_NAND, |
| 101 | NODE_QSPI, |
| 102 | NODE_GPIO, |
| 103 | NODE_CAN_0, |
| 104 | NODE_CAN_1, |
| 105 | NODE_EXTERN, |
| 106 | NODE_APLL, |
| 107 | NODE_VPLL, |
| 108 | NODE_DPLL, |
| 109 | NODE_RPLL, |
| 110 | NODE_IOPLL, |
| 111 | NODE_DDR, |
| 112 | NODE_IPI_APU, |
| 113 | NODE_IPI_RPU_0, |
| 114 | NODE_GPU, |
| 115 | NODE_PCIE, |
| 116 | NODE_PCAP, |
| 117 | NODE_RTC, |
| 118 | NODE_LPD, |
| 119 | NODE_VCU, |
| 120 | NODE_IPI_RPU_1, |
| 121 | NODE_IPI_PL_0, |
| 122 | NODE_IPI_PL_1, |
| 123 | NODE_IPI_PL_2, |
| 124 | NODE_IPI_PL_3, |
| 125 | NODE_PL, |
| 126 | NODE_GEM_TSU, |
| 127 | NODE_SWDT_0, |
| 128 | NODE_SWDT_1, |
| 129 | NODE_CSU, |
| 130 | NODE_PJTAG, |
| 131 | NODE_TRACE, |
| 132 | NODE_TESTSCAN, |
| 133 | NODE_PMU, |
| 134 | NODE_MAX, |
| 135 | }; |
| 136 | |
| 137 | enum pm_request_ack { |
| 138 | REQ_ACK_NO = 1, |
| 139 | REQ_ACK_BLOCKING, |
| 140 | REQ_ACK_NON_BLOCKING, |
| 141 | }; |
| 142 | |
| 143 | enum pm_suspend_reason { |
| 144 | SUSPEND_REASON_PU_REQ = 201, |
| 145 | SUSPEND_REASON_ALERT, |
| 146 | SUSPEND_REASON_SYS_SHUTDOWN, |
| 147 | }; |
| 148 | |
| 149 | enum pm_ram_state { |
| 150 | PM_RAM_STATE_OFF = 1, |
| 151 | PM_RAM_STATE_RETENTION, |
| 152 | PM_RAM_STATE_ON, |
| 153 | }; |
| 154 | |
| 155 | /** |
| 156 | * @PM_INITIAL_BOOT: boot is a fresh system startup |
| 157 | * @PM_RESUME: boot is a resume |
| 158 | * @PM_BOOT_ERROR: error, boot cause cannot be identified |
| 159 | */ |
| 160 | enum pm_boot_status { |
| 161 | PM_INITIAL_BOOT, |
| 162 | PM_RESUME, |
| 163 | PM_BOOT_ERROR, |
| 164 | }; |
| 165 | |
| 166 | /** |
| 167 | * @PMF_SHUTDOWN_TYPE_SHUTDOWN: shutdown |
| 168 | * @PMF_SHUTDOWN_TYPE_RESET: reset/reboot |
| 169 | * @PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY: set the shutdown/reboot scope |
| 170 | */ |
| 171 | enum pm_shutdown_type { |
| 172 | PMF_SHUTDOWN_TYPE_SHUTDOWN, |
| 173 | PMF_SHUTDOWN_TYPE_RESET, |
| 174 | PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY, |
| 175 | }; |
| 176 | |
| 177 | /** |
| 178 | * @PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM: shutdown/reboot APU subsystem only |
| 179 | * @PMF_SHUTDOWN_SUBTYPE_PS_ONLY: shutdown/reboot entire PS (but not PL) |
| 180 | * @PMF_SHUTDOWN_SUBTYPE_SYSTEM: shutdown/reboot entire system |
| 181 | */ |
| 182 | enum pm_shutdown_subtype { |
| 183 | PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM, |
| 184 | PMF_SHUTDOWN_SUBTYPE_PS_ONLY, |
| 185 | PMF_SHUTDOWN_SUBTYPE_SYSTEM, |
| 186 | }; |
| 187 | |
| 188 | /** |
| 189 | * @PM_PLL_MODE_RESET: PLL is in reset (not locked) |
| 190 | * @PM_PLL_MODE_INTEGER: PLL is locked in integer mode |
| 191 | * @PM_PLL_MODE_FRACTIONAL: PLL is locked in fractional mode |
| 192 | */ |
| 193 | enum pm_pll_mode { |
| 194 | PM_PLL_MODE_RESET, |
| 195 | PM_PLL_MODE_INTEGER, |
| 196 | PM_PLL_MODE_FRACTIONAL, |
| 197 | PM_PLL_MODE_MAX, |
| 198 | }; |
| 199 | |
| 200 | /** |
| 201 | * @PM_CLOCK_DIV0_ID: Clock divider 0 |
| 202 | * @PM_CLOCK_DIV1_ID: Clock divider 1 |
| 203 | */ |
| 204 | enum pm_clock_div_id { |
| 205 | PM_CLOCK_DIV0_ID, |
| 206 | PM_CLOCK_DIV1_ID, |
| 207 | }; |
| 208 | |
| 209 | #endif /* ZYNQMP_PM_DEFS_H */ |