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Achin Gupta7c88f3f2014-02-18 18:09:12 +00001/*
Soby Mathewda43b662015-07-08 21:45:46 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta7c88f3f2014-02-18 18:09:12 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta7c88f3f2014-02-18 18:09:12 +000031#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000032#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <tsp.h>
Achin Guptae1aa5162014-06-26 09:58:52 +010034#include <xlat_tables.h>
Dan Handleye2c27f52014-08-01 17:58:27 +010035#include "../tsp_private.h"
Achin Gupta7c88f3f2014-02-18 18:09:12 +000036
37
38 .globl tsp_entrypoint
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010039 .globl tsp_vector_table
Achin Gupta7c88f3f2014-02-18 18:09:12 +000040
Soby Mathew9f71f702014-05-09 20:49:17 +010041
42
Achin Gupta7c88f3f2014-02-18 18:09:12 +000043 /* ---------------------------------------------
44 * Populate the params in x0-x7 from the pointer
45 * to the smc args structure in x0.
46 * ---------------------------------------------
47 */
48 .macro restore_args_call_smc
49 ldp x6, x7, [x0, #TSP_ARG6]
50 ldp x4, x5, [x0, #TSP_ARG4]
51 ldp x2, x3, [x0, #TSP_ARG2]
52 ldp x0, x1, [x0, #TSP_ARG0]
53 smc #0
54 .endm
55
Achin Gupta76717892014-05-09 11:42:56 +010056 .macro save_eret_context reg1 reg2
57 mrs \reg1, elr_el1
58 mrs \reg2, spsr_el1
59 stp \reg1, \reg2, [sp, #-0x10]!
60 stp x30, x18, [sp, #-0x10]!
61 .endm
62
63 .macro restore_eret_context reg1 reg2
64 ldp x30, x18, [sp], #0x10
65 ldp \reg1, \reg2, [sp], #0x10
66 msr elr_el1, \reg1
67 msr spsr_el1, \reg2
68 .endm
69
70 .section .text, "ax"
71 .align 3
Achin Gupta7c88f3f2014-02-18 18:09:12 +000072
Andrew Thoelke38bde412014-03-18 13:46:55 +000073func tsp_entrypoint
Achin Gupta7c88f3f2014-02-18 18:09:12 +000074
75 /* ---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +000076 * Set the exception vector to something sane.
77 * ---------------------------------------------
78 */
Achin Guptaa4f50c22014-05-09 12:17:56 +010079 adr x0, tsp_exceptions
Achin Gupta7c88f3f2014-02-18 18:09:12 +000080 msr vbar_el1, x0
Achin Guptaed1744e2014-08-04 23:13:10 +010081 isb
Achin Gupta7c88f3f2014-02-18 18:09:12 +000082
83 /* ---------------------------------------------
Achin Guptaed1744e2014-08-04 23:13:10 +010084 * Enable the SError interrupt now that the
85 * exception vectors have been setup.
86 * ---------------------------------------------
87 */
88 msr daifclr, #DAIF_ABT_BIT
89
90 /* ---------------------------------------------
Achin Gupta9f098352014-07-18 18:38:28 +010091 * Enable the instruction cache, stack pointer
92 * and data access alignment checks
Achin Gupta7c88f3f2014-02-18 18:09:12 +000093 * ---------------------------------------------
94 */
Achin Gupta9f098352014-07-18 18:38:28 +010095 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
Achin Gupta7c88f3f2014-02-18 18:09:12 +000096 mrs x0, sctlr_el1
Achin Gupta9f098352014-07-18 18:38:28 +010097 orr x0, x0, x1
Achin Gupta7c88f3f2014-02-18 18:09:12 +000098 msr sctlr_el1, x0
99 isb
100
101 /* ---------------------------------------------
Achin Guptae9c4a642015-09-11 16:03:13 +0100102 * Invalidate the RW memory used by the BL32
103 * image. This includes the data and NOBITS
104 * sections. This is done to safeguard against
105 * possible corruption of this memory by dirty
106 * cache lines in a system cache as a result of
107 * use by an earlier boot loader stage.
108 * ---------------------------------------------
109 */
110 adr x0, __RW_START__
111 adr x1, __RW_END__
112 sub x1, x1, x0
113 bl inv_dcache_range
114
115 /* ---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000116 * Zero out NOBITS sections. There are 2 of them:
117 * - the .bss section;
118 * - the coherent memory section.
119 * ---------------------------------------------
120 */
121 ldr x0, =__BSS_START__
122 ldr x1, =__BSS_SIZE__
123 bl zeromem16
124
Soby Mathew2ae20432015-01-08 18:02:44 +0000125#if USE_COHERENT_MEM
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000126 ldr x0, =__COHERENT_RAM_START__
127 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
128 bl zeromem16
Soby Mathew2ae20432015-01-08 18:02:44 +0000129#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000130
131 /* --------------------------------------------
Achin Guptaf4a97092014-06-25 19:26:22 +0100132 * Allocate a stack whose memory will be marked
133 * as Normal-IS-WBWA when the MMU is enabled.
134 * There is no risk of reading stale stack
135 * memory after enabling the MMU as only the
136 * primary cpu is running at the moment.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000137 * --------------------------------------------
138 */
Soby Mathewda43b662015-07-08 21:45:46 +0100139 bl plat_set_my_stack
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000140
141 /* ---------------------------------------------
142 * Perform early platform setup & platform
143 * specific early arch. setup e.g. mmu setup
144 * ---------------------------------------------
145 */
Dan Handley4fd2f5c2014-08-04 11:41:20 +0100146 bl tsp_early_platform_setup
147 bl tsp_plat_arch_setup
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000148
149 /* ---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000150 * Jump to main function.
151 * ---------------------------------------------
152 */
153 bl tsp_main
154
155 /* ---------------------------------------------
156 * Tell TSPD that we are done initialising
157 * ---------------------------------------------
158 */
159 mov x1, x0
160 mov x0, #TSP_ENTRY_DONE
161 smc #0
162
163tsp_entrypoint_panic:
164 b tsp_entrypoint_panic
Kévin Petita877c252015-03-24 14:03:57 +0000165endfunc tsp_entrypoint
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000166
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100167
168 /* -------------------------------------------
169 * Table of entrypoint vectors provided to the
170 * TSPD for the various entrypoints
171 * -------------------------------------------
172 */
173func tsp_vector_table
174 b tsp_std_smc_entry
175 b tsp_fast_smc_entry
176 b tsp_cpu_on_entry
177 b tsp_cpu_off_entry
178 b tsp_cpu_resume_entry
179 b tsp_cpu_suspend_entry
Soby Mathewbec98512015-09-03 18:29:38 +0100180 b tsp_sel1_intr_entry
Juan Castillo4dc4a472014-08-12 11:17:06 +0100181 b tsp_system_off_entry
182 b tsp_system_reset_entry
Kévin Petita877c252015-03-24 14:03:57 +0000183endfunc tsp_vector_table
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100184
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000185 /*---------------------------------------------
186 * This entrypoint is used by the TSPD when this
187 * cpu is to be turned off through a CPU_OFF
188 * psci call to ask the TSP to perform any
189 * bookeeping necessary. In the current
190 * implementation, the TSPD expects the TSP to
191 * re-initialise its state so nothing is done
192 * here except for acknowledging the request.
193 * ---------------------------------------------
194 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000195func tsp_cpu_off_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000196 bl tsp_cpu_off_main
197 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000198endfunc tsp_cpu_off_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000199
200 /*---------------------------------------------
Juan Castillo4dc4a472014-08-12 11:17:06 +0100201 * This entrypoint is used by the TSPD when the
202 * system is about to be switched off (through
203 * a SYSTEM_OFF psci call) to ask the TSP to
204 * perform any necessary bookkeeping.
205 * ---------------------------------------------
206 */
207func tsp_system_off_entry
208 bl tsp_system_off_main
209 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000210endfunc tsp_system_off_entry
Juan Castillo4dc4a472014-08-12 11:17:06 +0100211
212 /*---------------------------------------------
213 * This entrypoint is used by the TSPD when the
214 * system is about to be reset (through a
215 * SYSTEM_RESET psci call) to ask the TSP to
216 * perform any necessary bookkeeping.
217 * ---------------------------------------------
218 */
219func tsp_system_reset_entry
220 bl tsp_system_reset_main
221 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000222endfunc tsp_system_reset_entry
Juan Castillo4dc4a472014-08-12 11:17:06 +0100223
224 /*---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000225 * This entrypoint is used by the TSPD when this
226 * cpu is turned on using a CPU_ON psci call to
227 * ask the TSP to initialise itself i.e. setup
228 * the mmu, stacks etc. Minimal architectural
229 * state will be initialised by the TSPD when
230 * this function is entered i.e. Caches and MMU
231 * will be turned off, the execution state
232 * will be aarch64 and exceptions masked.
233 * ---------------------------------------------
234 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000235func tsp_cpu_on_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000236 /* ---------------------------------------------
237 * Set the exception vector to something sane.
238 * ---------------------------------------------
239 */
Achin Guptaa4f50c22014-05-09 12:17:56 +0100240 adr x0, tsp_exceptions
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000241 msr vbar_el1, x0
Achin Guptaed1744e2014-08-04 23:13:10 +0100242 isb
243
244 /* Enable the SError interrupt */
245 msr daifclr, #DAIF_ABT_BIT
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000246
247 /* ---------------------------------------------
Achin Gupta9f098352014-07-18 18:38:28 +0100248 * Enable the instruction cache, stack pointer
249 * and data access alignment checks
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000250 * ---------------------------------------------
251 */
Achin Gupta9f098352014-07-18 18:38:28 +0100252 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000253 mrs x0, sctlr_el1
Achin Gupta9f098352014-07-18 18:38:28 +0100254 orr x0, x0, x1
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000255 msr sctlr_el1, x0
256 isb
257
258 /* --------------------------------------------
Achin Guptae1aa5162014-06-26 09:58:52 +0100259 * Give ourselves a stack whose memory will be
260 * marked as Normal-IS-WBWA when the MMU is
261 * enabled.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000262 * --------------------------------------------
263 */
Soby Mathewda43b662015-07-08 21:45:46 +0100264 bl plat_set_my_stack
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000265
Achin Guptae1aa5162014-06-26 09:58:52 +0100266 /* --------------------------------------------
267 * Enable the MMU with the DCache disabled. It
268 * is safe to use stacks allocated in normal
269 * memory as a result. All memory accesses are
270 * marked nGnRnE when the MMU is disabled. So
271 * all the stack writes will make it to memory.
272 * All memory accesses are marked Non-cacheable
273 * when the MMU is enabled but D$ is disabled.
274 * So used stack memory is guaranteed to be
275 * visible immediately after the MMU is enabled
276 * Enabling the DCache at the same time as the
277 * MMU can lead to speculatively fetched and
278 * possibly stale stack memory being read from
279 * other caches. This can lead to coherency
280 * issues.
281 * --------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000282 */
Achin Guptae1aa5162014-06-26 09:58:52 +0100283 mov x0, #DISABLE_DCACHE
Dan Handleyb226a4d2014-05-16 14:08:45 +0100284 bl bl32_plat_enable_mmu
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000285
286 /* ---------------------------------------------
Achin Guptae1aa5162014-06-26 09:58:52 +0100287 * Enable the Data cache now that the MMU has
288 * been enabled. The stack has been unwound. It
289 * will be written first before being read. This
290 * will invalidate any stale cache lines resi-
291 * -dent in other caches. We assume that
292 * interconnect coherency has been enabled for
293 * this cluster by EL3 firmware.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000294 * ---------------------------------------------
295 */
Achin Guptae1aa5162014-06-26 09:58:52 +0100296 mrs x0, sctlr_el1
297 orr x0, x0, #SCTLR_C_BIT
298 msr sctlr_el1, x0
299 isb
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000300
301 /* ---------------------------------------------
302 * Enter C runtime to perform any remaining
303 * book keeping
304 * ---------------------------------------------
305 */
306 bl tsp_cpu_on_main
307 restore_args_call_smc
308
309 /* Should never reach here */
310tsp_cpu_on_entry_panic:
311 b tsp_cpu_on_entry_panic
Kévin Petita877c252015-03-24 14:03:57 +0000312endfunc tsp_cpu_on_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000313
314 /*---------------------------------------------
315 * This entrypoint is used by the TSPD when this
316 * cpu is to be suspended through a CPU_SUSPEND
317 * psci call to ask the TSP to perform any
318 * bookeeping necessary. In the current
319 * implementation, the TSPD saves and restores
320 * the EL1 state.
321 * ---------------------------------------------
322 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000323func tsp_cpu_suspend_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000324 bl tsp_cpu_suspend_main
325 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000326endfunc tsp_cpu_suspend_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000327
Soby Mathewbec98512015-09-03 18:29:38 +0100328 /*-------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100329 * This entrypoint is used by the TSPD to pass
Soby Mathew78664242015-11-13 02:08:43 +0000330 * control for `synchronously` handling a S-EL1
331 * Interrupt which was triggered while executing
332 * in normal world. 'x0' contains a magic number
333 * which indicates this. TSPD expects control to
334 * be handed back at the end of interrupt
335 * processing. This is done through an SMC.
336 * The handover agreement is:
Achin Gupta76717892014-05-09 11:42:56 +0100337 *
338 * 1. PSTATE.DAIF are set upon entry. 'x1' has
339 * the ELR_EL3 from the non-secure state.
340 * 2. TSP has to preserve the callee saved
341 * general purpose registers, SP_EL1/EL0 and
342 * LR.
343 * 3. TSP has to preserve the system and vfp
344 * registers (if applicable).
345 * 4. TSP can use 'x0-x18' to enable its C
346 * runtime.
347 * 5. TSP returns to TSPD using an SMC with
Soby Mathewbec98512015-09-03 18:29:38 +0100348 * 'x0' = TSP_HANDLED_S_EL1_INTR
349 * ------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100350 */
Soby Mathewbec98512015-09-03 18:29:38 +0100351func tsp_sel1_intr_entry
Achin Gupta76717892014-05-09 11:42:56 +0100352#if DEBUG
Soby Mathew78664242015-11-13 02:08:43 +0000353 mov_imm x2, TSP_HANDLE_SEL1_INTR_AND_RETURN
Achin Gupta76717892014-05-09 11:42:56 +0100354 cmp x0, x2
Soby Mathewbec98512015-09-03 18:29:38 +0100355 b.ne tsp_sel1_int_entry_panic
Achin Gupta76717892014-05-09 11:42:56 +0100356#endif
Soby Mathewbec98512015-09-03 18:29:38 +0100357 /*-------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100358 * Save any previous context needed to perform
359 * an exception return from S-EL1 e.g. context
Soby Mathewbec98512015-09-03 18:29:38 +0100360 * from a previous Non secure Interrupt.
361 * Update statistics and handle the S-EL1
362 * interrupt before returning to the TSPD.
Achin Gupta76717892014-05-09 11:42:56 +0100363 * IRQ/FIQs are not enabled since that will
364 * complicate the implementation. Execution
365 * will be transferred back to the normal world
Soby Mathew78664242015-11-13 02:08:43 +0000366 * in any case. The handler can return 0
367 * if the interrupt was handled or TSP_PREEMPTED
368 * if the expected interrupt was preempted
369 * by an interrupt that should be handled in EL3
370 * e.g. Group 0 interrupt in GICv3. In both
371 * the cases switch to EL3 using SMC with id
372 * TSP_HANDLED_S_EL1_INTR. Any other return value
373 * from the handler will result in panic.
Soby Mathewbec98512015-09-03 18:29:38 +0100374 * ------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100375 */
376 save_eret_context x2 x3
Soby Mathewbec98512015-09-03 18:29:38 +0100377 bl tsp_update_sync_sel1_intr_stats
378 bl tsp_common_int_handler
Soby Mathew78664242015-11-13 02:08:43 +0000379 /* Check if the S-EL1 interrupt has been handled */
380 cbnz x0, tsp_sel1_intr_check_preemption
381 b tsp_sel1_intr_return
382tsp_sel1_intr_check_preemption:
383 /* Check if the S-EL1 interrupt has been preempted */
384 mov_imm x1, TSP_PREEMPTED
385 cmp x0, x1
386 b.ne tsp_sel1_int_entry_panic
387tsp_sel1_intr_return:
388 mov_imm x0, TSP_HANDLED_S_EL1_INTR
Achin Gupta76717892014-05-09 11:42:56 +0100389 restore_eret_context x2 x3
Achin Gupta76717892014-05-09 11:42:56 +0100390 smc #0
391
Soby Mathew78664242015-11-13 02:08:43 +0000392 /* Should never reach here */
Soby Mathewbec98512015-09-03 18:29:38 +0100393tsp_sel1_int_entry_panic:
394 b tsp_sel1_int_entry_panic
395endfunc tsp_sel1_intr_entry
Achin Gupta76717892014-05-09 11:42:56 +0100396
397 /*---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000398 * This entrypoint is used by the TSPD when this
399 * cpu resumes execution after an earlier
400 * CPU_SUSPEND psci call to ask the TSP to
401 * restore its saved context. In the current
402 * implementation, the TSPD saves and restores
403 * EL1 state so nothing is done here apart from
404 * acknowledging the request.
405 * ---------------------------------------------
406 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000407func tsp_cpu_resume_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000408 bl tsp_cpu_resume_main
409 restore_args_call_smc
410tsp_cpu_resume_panic:
411 b tsp_cpu_resume_panic
Kévin Petita877c252015-03-24 14:03:57 +0000412endfunc tsp_cpu_resume_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000413
414 /*---------------------------------------------
415 * This entrypoint is used by the TSPD to ask
416 * the TSP to service a fast smc request.
417 * ---------------------------------------------
418 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000419func tsp_fast_smc_entry
Soby Mathew9f71f702014-05-09 20:49:17 +0100420 bl tsp_smc_handler
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000421 restore_args_call_smc
422tsp_fast_smc_entry_panic:
423 b tsp_fast_smc_entry_panic
Kévin Petita877c252015-03-24 14:03:57 +0000424endfunc tsp_fast_smc_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000425
Soby Mathew9f71f702014-05-09 20:49:17 +0100426 /*---------------------------------------------
427 * This entrypoint is used by the TSPD to ask
428 * the TSP to service a std smc request.
429 * We will enable preemption during execution
430 * of tsp_smc_handler.
431 * ---------------------------------------------
432 */
433func tsp_std_smc_entry
434 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
435 bl tsp_smc_handler
436 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
437 restore_args_call_smc
438tsp_std_smc_entry_panic:
439 b tsp_std_smc_entry_panic
Kévin Petita877c252015-03-24 14:03:57 +0000440endfunc tsp_std_smc_entry