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Haojian Zhuang1b5c2252017-06-01 15:20:46 +08001/*
Lukas Hanel5258be12022-03-01 17:02:31 +01002 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang1b5c2252017-06-01 15:20:46 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Haojian Zhuang1b5c2252017-06-01 15:20:46 +08007#include <assert.h>
Haojian Zhuang1b5c2252017-06-01 15:20:46 +08008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080010#include <platform_def.h>
11
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <arch_helpers.h>
13#include <bl31/interrupt_mgmt.h>
14#include <common/bl_common.h>
15#include <common/debug.h>
16#include <common/interrupt_props.h>
17#include <drivers/arm/cci.h>
18#include <drivers/arm/gicv2.h>
19#include <drivers/arm/pl011.h>
20#include <drivers/console.h>
21#include <drivers/generic_delay_timer.h>
22#include <lib/mmio.h>
Lukas Hanel5258be12022-03-01 17:02:31 +010023#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <plat/common/platform.h>
vallau01538a6df2022-08-02 16:16:11 +020025#include <services/el3_spmc_ffa_memory.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000026
27#include <hi3660.h>
28#include <hisi_ipc.h>
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080029#include "hikey960_def.h"
30#include "hikey960_private.h"
31
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080032static entry_point_info_t bl32_ep_info;
33static entry_point_info_t bl33_ep_info;
Andre Przywara2b1b1a52020-01-25 00:58:35 +000034static console_t console;
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080035
Arthur Cassegrain97d4d812021-11-26 16:39:12 +010036/* fastboot serial number consumed by Kinibi SPD/LP for gpd.tee.deviceID. */
37uint64_t fastboot_serno;
38
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080039/******************************************************************************
40 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
41 * interrupts.
42 *****************************************************************************/
Antonio Nino Diaz582c2d72018-09-24 17:23:47 +010043static const interrupt_prop_t g0_interrupt_props[] = {
44 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
45 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
46 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
47 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080048};
49
50const gicv2_driver_data_t hikey960_gic_data = {
51 .gicd_base = GICD_REG_BASE,
52 .gicc_base = GICC_REG_BASE,
Antonio Nino Diaz582c2d72018-09-24 17:23:47 +010053 .interrupt_props = g0_interrupt_props,
54 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080055};
56
57static const int cci_map[] = {
58 CCI400_SL_IFACE3_CLUSTER_IX,
59 CCI400_SL_IFACE4_CLUSTER_IX
60};
61
Victor Chong7d787f52017-08-16 13:53:56 +090062entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080063{
64 entry_point_info_t *next_image_info;
65
66 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
67
68 /* None of the images on this platform can have 0x0 as the entrypoint */
69 if (next_image_info->pc)
70 return next_image_info;
71 return NULL;
72}
73
Antonio Nino Diaz582c2d72018-09-24 17:23:47 +010074void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
75 u_register_t arg2, u_register_t arg3)
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080076{
77 unsigned int id, uart_base;
Antonio Nino Diaz582c2d72018-09-24 17:23:47 +010078 void *from_bl2;
Arthur Cassegrain97d4d812021-11-26 16:39:12 +010079 plat_params_from_bl2_t *plat_params_from_bl2 = (plat_params_from_bl2_t *) arg1;
Antonio Nino Diaz582c2d72018-09-24 17:23:47 +010080
81 from_bl2 = (void *) arg0;
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080082
83 generic_delay_timer_init();
84 hikey960_read_boardid(&id);
85 if (id == 5300)
86 uart_base = PL011_UART5_BASE;
87 else
88 uart_base = PL011_UART6_BASE;
89
90 /* Initialize the console to provide early debug support */
Jerome Forissier3fb19df2018-11-08 09:59:29 +010091 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ,
92 PL011_BAUDRATE, &console);
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080093
94 /* Initialize CCI driver */
95 cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map));
96 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
97
Arthur Cassegrain97d4d812021-11-26 16:39:12 +010098 /* Fastboot serial number passed from BL2 as a platform parameter */
99 fastboot_serno = plat_params_from_bl2->fastboot_serno;
100 INFO("BL31: fastboot_serno %lx\n", fastboot_serno);
101
Victor Chong2d9a42d2017-08-17 15:21:10 +0900102 /*
103 * Check params passed from BL2 should not be NULL,
104 */
105 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
106 assert(params_from_bl2 != NULL);
107 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
108 assert(params_from_bl2->h.version >= VERSION_2);
109
110 bl_params_node_t *bl_params = params_from_bl2->head;
111
112 /*
113 * Copy BL33 and BL32 (if present), entry point information.
114 * They are stored in Secure RAM, in BL2's address space.
115 */
116 while (bl_params) {
117 if (bl_params->image_id == BL32_IMAGE_ID)
118 bl32_ep_info = *bl_params->ep_info;
119
120 if (bl_params->image_id == BL33_IMAGE_ID)
121 bl33_ep_info = *bl_params->ep_info;
122
123 bl_params = bl_params->next_params_info;
124 }
125
126 if (bl33_ep_info.pc == 0)
127 panic();
Haojian Zhuang1b5c2252017-06-01 15:20:46 +0800128}
129
130void bl31_plat_arch_setup(void)
131{
Lukas Hanel5258be12022-03-01 17:02:31 +0100132#if SPMC_AT_EL3
133 mmap_add_region(DDR2_SEC_BASE, DDR2_SEC_BASE, DDR2_SEC_SIZE,
134 MT_MEMORY | MT_RW | MT_SECURE);
135#endif
136
Haojian Zhuang1b5c2252017-06-01 15:20:46 +0800137 hikey960_init_mmu_el3(BL31_BASE,
138 BL31_LIMIT - BL31_BASE,
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000139 BL_CODE_BASE,
140 BL_CODE_END,
141 BL_COHERENT_RAM_BASE,
142 BL_COHERENT_RAM_END);
Haojian Zhuang1b5c2252017-06-01 15:20:46 +0800143}
144
Ryan Grachek44f8d652018-11-29 12:45:55 -0600145static void hikey960_edma_init(void)
146{
147 int i;
148 uint32_t non_secure;
149
150 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC;
151 mmio_write_32(EDMAC_SEC_CTRL, non_secure);
152
Ryan Gracheke2713b62019-01-11 08:33:00 -0600153 /* Channel 0 is reserved for LPM3, keep secure */
154 for (i = 1; i < EDMAC_CHANNEL_NUMS; i++) {
Ryan Grachek44f8d652018-11-29 12:45:55 -0600155 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
156 }
157}
158
Ryan Grachek62a84ed2019-02-11 10:22:24 -0600159static void hikey960_iomcu_dma_init(void)
160{
161 int i;
162 uint32_t non_secure;
163
164 non_secure = IOMCU_DMAC_SEC_CTRL_INTR_SEC | IOMCU_DMAC_SEC_CTRL_GLOBAL_SEC;
165 mmio_write_32(IOMCU_DMAC_SEC_CTRL, non_secure);
166
167 /* channels 0-3 are reserved */
168 for (i = 4; i < IOMCU_DMAC_CHANNEL_NUMS; i++) {
169 mmio_write_32(IOMCU_DMAC_AXI_CONF(i), IOMCU_DMAC_AXI_CONF_ARPROT_NS |
170 IOMCU_DMAC_AXI_CONF_AWPROT_NS);
171 }
172}
Lukas Hanel5258be12022-03-01 17:02:31 +0100173
174#if SPMC_AT_EL3
175/*
176 * On the hikey960 platform when using the EL3 SPMC implementation allocate the
177 * datastore for tracking shared memory descriptors in the RAM2 DRAM section
178 * to ensure sufficient storage can be allocated.
179 * Provide an implementation of the accessor method to allow the datastore
180 * details to be retrieved by the SPMC.
181 * The SPMC will take care of initializing the memory region.
182 */
183
184#define SPMC_SHARED_MEMORY_OBJ_SIZE (512 * 1024)
185
Chris Kay33bfc5e2023-02-14 11:30:04 +0000186__section(".ram2_region") uint8_t plat_spmc_shmem_datastore[SPMC_SHARED_MEMORY_OBJ_SIZE];
Lukas Hanel5258be12022-03-01 17:02:31 +0100187
188int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size)
189{
190 *datastore = plat_spmc_shmem_datastore;
191 *size = SPMC_SHARED_MEMORY_OBJ_SIZE;
192 return 0;
193}
vallau01538a6df2022-08-02 16:16:11 +0200194
195/*
196 * Add dummy implementations of memory management related platform hooks.
197 * These can be used to implement platform specific functionality to support
198 * a memory sharing/lending operation.
199 *
200 * Note: The hooks must be located as part of the initial share request and
201 * final reclaim to prevent order dependencies with operations that may take
202 * place in the normal world without visibility of the SPMC.
203 */
204int plat_spmc_shmem_begin(struct ffa_mtd *desc)
205{
206 return 0;
207}
208
209int plat_spmc_shmem_reclaim(struct ffa_mtd *desc)
210{
211 return 0;
212}
213
Lukas Hanel5258be12022-03-01 17:02:31 +0100214#endif
Ryan Grachek62a84ed2019-02-11 10:22:24 -0600215
Haojian Zhuang1b5c2252017-06-01 15:20:46 +0800216void bl31_platform_setup(void)
217{
218 /* Initialize the GIC driver, cpu and distributor interfaces */
219 gicv2_driver_init(&hikey960_gic_data);
220 gicv2_distif_init();
221 gicv2_pcpu_distif_init();
222 gicv2_cpuif_enable();
223
Ryan Grachek44f8d652018-11-29 12:45:55 -0600224 hikey960_edma_init();
Ryan Grachek62a84ed2019-02-11 10:22:24 -0600225 hikey960_iomcu_dma_init();
Leo Yan3886dc62020-03-02 22:15:08 +0800226 hikey960_gpio_init();
Ryan Grachek44f8d652018-11-29 12:45:55 -0600227
Haojian Zhuang1b5c2252017-06-01 15:20:46 +0800228 hisi_ipc_init();
229}
230
Leo Yanaf316a32018-01-22 12:40:25 +0800231#ifdef SPD_none
232static uint64_t hikey_debug_fiq_handler(uint32_t id,
233 uint32_t flags,
234 void *handle,
235 void *cookie)
236{
237 int intr, intr_raw;
238
239 /* Acknowledge interrupt */
240 intr_raw = plat_ic_acknowledge_interrupt();
241 intr = plat_ic_get_interrupt_id(intr_raw);
242 ERROR("Invalid interrupt: intr=%d\n", intr);
243 console_flush();
244 panic();
245
246 return 0;
247}
248#endif
249
Haojian Zhuang1b5c2252017-06-01 15:20:46 +0800250void bl31_plat_runtime_setup(void)
251{
Leo Yanaf316a32018-01-22 12:40:25 +0800252#ifdef SPD_none
253 uint32_t flags;
254 int32_t rc;
255
256 flags = 0;
257 set_interrupt_rm_flag(flags, NON_SECURE);
258 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1,
259 hikey_debug_fiq_handler,
260 flags);
261 if (rc != 0)
262 panic();
263#endif
Haojian Zhuang1b5c2252017-06-01 15:20:46 +0800264}