Boyan Karatotev | 05504ba | 2023-02-15 13:21:50 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2023, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_features.h> |
| 9 | #include <arch_helpers.h> |
| 10 | #include <lib/extensions/pmuv3.h> |
| 11 | |
| 12 | static u_register_t init_mdcr_el2_hpmn(u_register_t mdcr_el2) |
| 13 | { |
| 14 | /* |
| 15 | * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't |
| 16 | * throw anyone off who expects this to be sensible. |
| 17 | */ |
| 18 | mdcr_el2 &= ~MDCR_EL2_HPMN_MASK; |
| 19 | mdcr_el2 |= ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & PMCR_EL0_N_MASK); |
| 20 | |
| 21 | return mdcr_el2; |
| 22 | } |
| 23 | |
| 24 | void pmuv3_enable(cpu_context_t *ctx) |
| 25 | { |
| 26 | #if CTX_INCLUDE_EL2_REGS |
| 27 | u_register_t mdcr_el2; |
| 28 | |
| 29 | mdcr_el2 = read_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2); |
| 30 | mdcr_el2 = init_mdcr_el2_hpmn(mdcr_el2); |
| 31 | write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); |
| 32 | #endif /* CTX_INCLUDE_EL2_REGS */ |
| 33 | } |
| 34 | |
| 35 | void pmuv3_disable_el3(void) |
| 36 | { |
| 37 | u_register_t mdcr_el3 = read_mdcr_el3(); |
| 38 | |
| 39 | /* --------------------------------------------------------------------- |
| 40 | * Initialise MDCR_EL3, setting all fields rather than relying on hw. |
| 41 | * Some fields are architecturally UNKNOWN on reset. |
| 42 | * |
| 43 | * MDCR_EL3.MPMX: Set to zero to not affect event counters (when |
| 44 | * SPME = 0). |
| 45 | * |
| 46 | * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is |
| 47 | * prohibited in EL3. This bit is RES0 in versions of the |
| 48 | * architecture with FEAT_PMUv3p7 not implemented. |
| 49 | * |
| 50 | * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is |
| 51 | * prohibited in Secure state. This bit is RES0 in versions of the |
| 52 | * architecture with FEAT_PMUv3p5 not implemented. |
| 53 | * |
| 54 | * MDCR_EL3.SPME: Set to zero so that event counting is prohibited in |
| 55 | * Secure state (and explicitly EL3 with later revisions). If ARMv8.2 |
| 56 | * Debug is not implemented this bit does not have any effect on the |
| 57 | * counters unless there is support for the implementation defined |
| 58 | * authentication interface ExternalSecureNoninvasiveDebugEnabled(). |
| 59 | * |
| 60 | * The SPME/MPMX combination is a little tricky. Below is a small |
| 61 | * summary if another combination is ever needed: |
| 62 | * SPME | MPMX | secure world | EL3 |
| 63 | * ------------------------------------- |
| 64 | * 0 | 0 | disabled | disabled |
| 65 | * 1 | 0 | enabled | enabled |
| 66 | * 0 | 1 | enabled | disabled |
| 67 | * 1 | 1 | enabled | disabled only for counters 0 to |
| 68 | * MDCR_EL2.HPMN - 1. Enabled for the rest |
| 69 | */ |
| 70 | mdcr_el3 = (mdcr_el3 | MDCR_SCCD_BIT | MDCR_MCCD_BIT) & |
| 71 | ~(MDCR_MPMX_BIT | MDCR_SPME_BIT); |
| 72 | write_mdcr_el3(mdcr_el3); |
| 73 | |
| 74 | /* --------------------------------------------------------------------- |
| 75 | * Initialise PMCR_EL0 setting all fields rather than relying |
| 76 | * on hw. Some fields are architecturally UNKNOWN on reset. |
| 77 | * |
| 78 | * PMCR_EL0.DP: Set to one so that the cycle counter, |
| 79 | * PMCCNTR_EL0 does not count when event counting is prohibited. |
| 80 | * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not |
| 81 | * available |
| 82 | * |
| 83 | * PMCR_EL0.X: Set to zero to disable export of events. |
| 84 | * |
| 85 | * PMCR_EL0.C: Set to one to reset PMCCNTR_EL0 to zero. |
| 86 | * |
| 87 | * PMCR_EL0.P: Set to one to reset each event counter PMEVCNTR<n>_EL0 to |
| 88 | * zero. |
| 89 | * |
| 90 | * PMCR_EL0.E: Set to zero to disable cycle and event counters. |
| 91 | * --------------------------------------------------------------------- |
| 92 | */ |
| 93 | write_pmcr_el0((read_pmcr_el0() | PMCR_EL0_DP_BIT | PMCR_EL0_C_BIT | |
| 94 | PMCR_EL0_P_BIT) & ~(PMCR_EL0_X_BIT | PMCR_EL0_E_BIT)); |
| 95 | } |
| 96 | |
| 97 | void pmuv3_init_el2_unused(void) |
| 98 | { |
| 99 | u_register_t mdcr_el2 = read_mdcr_el2(); |
| 100 | |
| 101 | /* |
| 102 | * Initialise MDCR_EL2, setting all fields rather than |
| 103 | * relying on hw. Some fields are architecturally |
| 104 | * UNKNOWN on reset. |
| 105 | * |
| 106 | * MDCR_EL2.HLP: Set to one so that event counter overflow, that is |
| 107 | * recorded in PMOVSCLR_EL0[0-30], occurs on the increment that changes |
| 108 | * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is implemented. |
| 109 | * This bit is RES0 in versions of the architecture earlier than |
| 110 | * ARMv8.5, setting it to 1 doesn't have any effect on them. |
| 111 | * |
| 112 | * MDCR_EL2.HCCD: Set to one to prohibit cycle counting at EL2. This bit |
| 113 | * is RES0 in versions of the architecture with FEAT_PMUv3p5 not |
| 114 | * implemented. |
| 115 | * |
| 116 | * MDCR_EL2.HPMD: Set to one so that event counting is |
| 117 | * prohibited at EL2 for counter n < MDCR_EL2.HPMN. This bit is RES0 |
| 118 | * in versions of the architecture with FEAT_PMUv3p1 not implemented. |
| 119 | * |
| 120 | * MDCR_EL2.HPME: Set to zero to disable event counters for counters |
| 121 | * n >= MDCR_EL2.HPMN. |
| 122 | * |
| 123 | * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and |
| 124 | * EL1 accesses to all Performance Monitors registers |
| 125 | * are not trapped to EL2. |
| 126 | * |
| 127 | * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 |
| 128 | * and EL1 accesses to the PMCR_EL0 or PMCR are not |
| 129 | * trapped to EL2. |
| 130 | */ |
| 131 | mdcr_el2 = (mdcr_el2 | MDCR_EL2_HLP_BIT | MDCR_EL2_HPMD_BIT | |
| 132 | MDCR_EL2_HCCD_BIT) & |
| 133 | ~(MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | MDCR_EL2_TPMCR_BIT); |
| 134 | mdcr_el2 = init_mdcr_el2_hpmn(mdcr_el2); |
| 135 | write_mdcr_el2(mdcr_el2); |
| 136 | } |