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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Build Options
2=============
3
4The TF-A build system supports the following build options. Unless mentioned
5otherwise, these options are expected to be specified at the build command
6line and are not to be modified in any component makefiles. Note that the
7build system doesn't track dependency for build options. Therefore, if any of
8the build options are changed from a previous build, a clean build must be
9performed.
10
11.. _build_options_common:
12
13Common build options
14--------------------
15
16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
18 code having a smaller resulting size.
19
20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
22 directory containing the SP source, relative to the ``bl32/``; the directory
23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
24
johpow01fa59c6f2020-10-02 13:41:11 -050025- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return
26 zero at all but the highest implemented exception level. Reads from the
27 memory mapped view are unaffected by this control.
28
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010029- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
31 ``aarch64``.
32
Alexei Fedorov132e6652020-12-07 16:38:53 +000033- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies
34 one or more feature modifiers. This option has the form ``[no]feature+...``
35 and defaults to ``none``. It translates into compiler option
36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the
37 list of supported feature modifiers.
38
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010039- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
42 :ref:`Firmware Design`.
43
44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
47
48- ``BL2``: This is an optional build option which specifies the path to BL2
49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
50 built.
51
52- ``BL2U``: This is an optional build option which specifies the path to
53 BL2U image. In this case, the BL2U in TF-A will not be built.
54
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060055- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset
56 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
57 entrypoint) or 1 (CPU reset to BL2 entrypoint).
58 The default value is 0.
59
60- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3.
61 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be
62 true in a 4-world system where RESET_TO_BL2 is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010063
Balint Dobszay719ba9c2021-03-26 16:23:18 +010064- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the
65 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided.
66
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010067- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
68 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
69 the RW sections in RAM, while leaving the RO sections in place. This option
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060070 enable this use-case. For now, this option is only supported
71 when RESET_TO_BL2 is set to '1'.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010072
73- ``BL31``: This is an optional build option which specifies the path to
74 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
75 be built.
76
77- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
78 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
79 this file name will be used to save the key.
80
81- ``BL32``: This is an optional build option which specifies the path to
82 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
83 be built.
84
85- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
86 Trusted OS Extra1 image for the ``fip`` target.
87
88- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
89 Trusted OS Extra2 image for the ``fip`` target.
90
91- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
92 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
93 this file name will be used to save the key.
94
95- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
96 ``fip`` target in case TF-A BL2 is used.
97
98- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
99 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
100 this file name will be used to save the key.
101
102- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
103 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
104 If enabled, it is needed to use a compiler that supports the option
105 ``-mbranch-protection``. Selects the branch protection features to use:
106- 0: Default value turns off all types of branch protection
107- 1: Enables all types of branch protection features
108- 2: Return address signing to its standard level
109- 3: Extend the signing to include leaf functions
Alexei Fedorove039e482020-06-19 14:33:49 +0100110- 4: Turn on branch target identification mechanism
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100111
112 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
113 and resulting PAuth/BTI features.
114
115 +-------+--------------+-------+-----+
116 | Value | GCC option | PAuth | BTI |
117 +=======+==============+=======+=====+
118 | 0 | none | N | N |
119 +-------+--------------+-------+-----+
120 | 1 | standard | Y | Y |
121 +-------+--------------+-------+-----+
122 | 2 | pac-ret | Y | N |
123 +-------+--------------+-------+-----+
124 | 3 | pac-ret+leaf | Y | N |
125 +-------+--------------+-------+-----+
Alexei Fedorove039e482020-06-19 14:33:49 +0100126 | 4 | bti | N | Y |
127 +-------+--------------+-------+-----+
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100128
Manish Pandey34a305e2021-10-21 21:53:49 +0100129 This option defaults to 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100130 Note that Pointer Authentication is enabled for Non-secure world
131 irrespective of the value of this option if the CPU supports it.
132
133- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
134 compilation of each build. It must be set to a C string (including quotes
135 where applicable). Defaults to a string that contains the time and date of
136 the compilation.
137
138- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
139 build to be uniquely identified. Defaults to the current git commit id.
140
Grant Likely388248a2020-07-30 08:50:10 +0100141- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build``
142
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100143- ``CFLAGS``: Extra user options appended on the compiler's command line in
144 addition to the options set by the build system.
145
146- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
147 release several CPUs out of reset. It can take either 0 (several CPUs may be
148 brought up) or 1 (only one CPU will ever be brought up during cold reset).
149 Default is 0. If the platform always brings up a single CPU, there is no
150 need to distinguish between primary and secondary CPUs and the boot path can
151 be optimised. The ``plat_is_my_cpu_primary()`` and
152 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
153 to be implemented in this case.
154
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100155- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
156 Defaults to ``tbbr``.
157
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100158- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
159 register state when an unexpected exception occurs during execution of
160 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
161 this is only enabled for a debug build of the firmware.
162
163- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
164 certificate generation tool to create new keys in case no valid keys are
165 present or specified. Allowed options are '0' or '1'. Default is '1'.
166
167- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
168 the AArch32 system registers to be included when saving and restoring the
169 CPU context. The option must be set to 0 for AArch64-only platforms (that
170 is on hardware that does not implement AArch32, or at least not at EL1 and
171 higher ELs). Default value is 1.
172
173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
174 registers to be included when saving and restoring the CPU context. Default
175 is 0.
176
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000177- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension
178 registers in cpu context. This must be enabled, if the platform wants to use
179 this feature in the Secure world and MTE is enabled at ELX. This flag can
180 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
181 Default value is 0.
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +0100182
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000183- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV
184 registers to be saved/restored when entering/exiting an EL2 execution
185 context. This flag can take values 0 to 2, to align with the
186 ``FEATURE_DETECTION`` mechanism. Default value is 0.
187
188- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer
189 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers
190 to be included when saving and restoring the CPU context as part of world
191 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION``
192 mechanism. Default value is 0.
193
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100194 Note that Pointer Authentication is enabled for Non-secure world irrespective
195 of the value of this flag if the CPU supports it.
196
197- ``DEBUG``: Chooses between a debug and release build. It can take either 0
198 (release) or 1 (debug) as values. 0 is the default.
199
Sumit Garg392e4df2019-11-15 10:43:00 +0530200- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the
201 authenticated decryption algorithm to be used to decrypt firmware/s during
202 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of
203 this flag is ``none`` to disable firmware decryption which is an optional
Manish Pandey34a305e2021-10-21 21:53:49 +0100204 feature as per TBBR.
Sumit Garg392e4df2019-11-15 10:43:00 +0530205
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100206- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
207 of the binary image. If set to 1, then only the ELF image is built.
208 0 is the default.
209
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000210- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented
211 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms
212 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU,
213 check the latest Arm ARM.
214
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100215- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
216 Board Boot authentication at runtime. This option is meant to be enabled only
217 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
218 flag has to be enabled. 0 is the default.
219
220- ``E``: Boolean option to make warnings into errors. Default is 1.
221
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +0000222 When specifying higher warnings levels (``W=1`` and higher), this option
223 defaults to 0. This is done to encourage contributors to use them, as they
224 are expected to produce warnings that would otherwise fail the build. New
225 contributions are still expected to build with ``W=0`` and ``E=1`` (the
226 default).
227
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100228- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
229 the normal boot flow. It must specify the entry point address of the EL3
230 payload. Please refer to the "Booting an EL3 payload" section for more
231 details.
232
Chris Kay925fda42021-05-25 10:42:56 +0100233- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters
234 (also known as group 1 counters). These are implementation-defined counters,
235 and as such require additional platform configuration. Default is 0.
236
Chris Kayf11909f2021-08-19 11:21:52 +0100237- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which
238 allows platforms with auxiliary counters to describe them via the
239 ``HW_CONFIG`` device tree blob. Default is 0.
240
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100241- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
242 are compiled out. For debug builds, this option defaults to 1, and calls to
243 ``assert()`` are left in place. For release builds, this option defaults to 0
244 and calls to ``assert()`` function are compiled out. This option can be set
245 independently of ``DEBUG``. It can also be used to hide any auxiliary code
246 that is only required for the assertion and does not fit in the assertion
247 itself.
248
Alexei Fedorovb8f26e92020-02-06 17:11:03 +0000249- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100250 dumps or not. It is supported in both AArch64 and AArch32. However, in
251 AArch32 the format of the frame records are not defined in the AAPCS and they
252 are defined by the implementation. This implementation of backtrace only
253 supports the format used by GCC when T32 interworking is disabled. For this
254 reason enabling this option in AArch32 will force the compiler to only
255 generate A32 code. This option is enabled by default only in AArch64 debug
256 builds, but this behaviour can be overridden in each platform's Makefile or
257 in the build command line.
258
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000259- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit
260 extensions. This flag can take the values 0 to 2, to align with the
261 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature
262 available on v8.4 onwards. Some v8.2 implementations also implement an AMU
263 and this option can be used to enable this feature on those systems as well.
264 This flag can take the values 0 to 2, the default is 0.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000265
266- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1``
267 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6
268 onwards. This flag can take the values 0 to 2, to align with the
269 ``FEATURE_DETECTION`` mechanism. Default value is ``0``.
270
271- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2``
272 extension. It allows access to the SCXTNUM_EL2 (Software Context Number)
273 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an
274 optional feature available on Arm v8.0 onwards. This flag can take values
275 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
276 Default value is ``0``.
277
278- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent
279 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3.
280 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4
281 and upwards. This flag can take the values 0 to 2, to align with the
282 ``FEATURE_DETECTION`` mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000283
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000284- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000285 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer
286 Physical Offset register) during EL2 to EL3 context save/restore operations.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000287 Its a mandatory architectural feature and is enabled from v8.6 and upwards.
288 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
289 mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000290
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000291- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps)
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000292 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000293 Read Trap Register) during EL2 to EL3 context save/restore operations.
294 Its a mandatory architectural feature and is enabled from v8.6 and upwards.
295 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
296 mechanism. Default value is ``0``.
297
298- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to
299 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as
300 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a
301 mandatory architectural feature and is enabled from v8.7 and upwards. This
302 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
303 mechanism. Default value is ``0``.
304
305- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged
306 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a
307 permission fault for any privileged data access from EL1/EL2 to virtual
308 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a
309 mandatory architectural feature and is enabled from v8.1 and upwards. This
310 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
311 mechanism. Default value is ``0``.
312
313- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension.
314 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This
315 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400316 mechanism. Default value is ``0``.
317
318- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP``
319 extension. This feature is only supported in AArch64 state. This flag can
320 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
321 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from
322 Armv8.5 onwards.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000323
Andre Przywara46880dc2022-11-17 16:42:09 +0000324- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB``
325 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and
326 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or
327 later CPUs. It is enabled from v8.5 and upwards and if needed can be
328 overidden from platforms explicitly.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000329
330- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2)
331 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4.
332 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
333 mechanism. Default is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000334
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100335- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed
336 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature
337 available on Arm v8.6. This flag can take values 0 to 2, to align with the
338 ``FEATURE_DETECTION`` mechanism. Default is ``0``.
339
340 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets
341 delayed by the amount of value in ``TWED_DELAY``.
342
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000343- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization
344 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register
345 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory
346 architectural feature and is enabled from v8.1 and upwards. It can take
347 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
348 Default value is ``0``.
johpow01f91e59f2021-08-04 19:38:18 -0500349
Mark Brownc37eee72023-03-14 20:13:03 +0000350- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to
351 allow access to TCR2_EL2 (extended translation control) from EL2 as
352 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a
353 mandatory architectural feature and is enabled from v8.9 and upwards. This
354 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
355 mechanism. Default value is ``0``.
356
Mark Brown293a6612023-03-14 20:48:43 +0000357- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE
358 at EL2 and below, and context switch relevant registers. This flag
359 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
360 mechanism. Default value is ``0``.
361
362- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE
363 at EL2 and below, and context switch relevant registers. This flag
364 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
365 mechanism. Default value is ``0``.
366
367- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE
368 at EL2 and below, and context switch relevant registers. This flag
369 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
370 mechanism. Default value is ``0``.
371
372- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE
373 at EL2 and below, and context switch relevant registers. This flag
374 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
375 mechanism. Default value is ``0``.
376
Mark Brown326f2952023-03-14 21:33:04 +0000377- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to
378 allow use of Guarded Control Stack from EL2 as well as adding the GCS
379 registers to the EL2 context save/restore operations. This flag can take
380 the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
381 Default value is ``0``.
382
Sandrine Bailleux11427302019-12-17 09:38:08 +0100383- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
zelalem-aweked5f45272019-11-12 16:20:17 -0600384 support in GCC for TF-A. This option is currently only supported for
385 AArch64. Default is 0.
386
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000387- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100388 feature. MPAM is an optional Armv8.4 extension that enables various memory
389 system components and resources to define partitions; software running at
390 various ELs can assign themselves to desired partition to control their
391 performance aspects.
392
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000393 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
394 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to
395 access their own MPAM registers without trapping into EL3. This option
396 doesn't make use of partitioning in EL3, however. Platform initialisation
397 code should configure and use partitions in EL3 as required. This option
398 defaults to ``0``.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100399
Chris Kay03be39d2021-05-05 13:38:30 +0100400- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power
401 Mitigation Mechanism supported by certain Arm cores, which allows the SoC
402 firmware to detect and limit high activity events to assist in SoC processor
403 power domain dynamic power budgeting and limit the triggering of whole-rail
404 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``.
405
406- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which
407 allows platforms with cores supporting MPMM to describe them via the
408 ``HW_CONFIG`` device tree blob. Default is 0.
409
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100410- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
411 support within generic code in TF-A. This option is currently only supported
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600412 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and
413 in BL32 (SP_min) for AARCH32. Default is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100414
415- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
416 Measurement Framework(PMF). Default is 0.
417
418- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
419 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
420 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
421 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
422 software.
423
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000424- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm
425 Management Extension. This flag can take the values 0 to 2, to align with
426 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently
427 an experimental feature.
Zelalem Aweke4d37db82021-07-11 18:33:20 -0500428
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100429- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
430 instrumentation which injects timestamp collection points into TF-A to
431 allow runtime performance to be measured. Currently, only PSCI is
432 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
433 as well. Default is 0.
434
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000435- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension
johpow019baade32021-07-08 14:14:00 -0500436 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share
437 registers so are enabled together. Using this option without
438 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000439 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a
440 superset of SVE. SME is an optional architectural feature for AArch64
johpow019baade32021-07-08 14:14:00 -0500441 and TF-A support is experimental. At this time, this build option cannot be
Manish Pandey247e5c32021-11-15 15:29:08 +0000442 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000443 build with these options will fail. This flag can take the values 0 to 2, to
444 align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
johpow019baade32021-07-08 14:14:00 -0500445
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000446- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension
447 version 2 (SME2) for the non-secure world only. SME2 is an optional
448 architectural feature for AArch64 and TF-A support is experimental.
449 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME
450 accesses will still be trapped. This flag can take the values 0 to 2, to
451 align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
452
johpow019baade32021-07-08 14:14:00 -0500453- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000454 Extension for secure world. Used along with SVE and FPU/SIMD.
455 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this.
456 This is experimental. Default is 0.
johpow019baade32021-07-08 14:14:00 -0500457
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +0000458- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100459 extensions. This is an optional architectural feature for AArch64.
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +0000460 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
461 mechanism. The default is 2 but is automatically disabled when the target
462 architecture is AArch32.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100463
Jayanth Dodderi Chidanandd62c6812023-03-07 10:43:19 +0000464- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100465 (SVE) for the Non-secure world only. SVE is an optional architectural feature
466 for AArch64. Note that when SVE is enabled for the Non-secure world, access
Max Shvetsovc4502772021-03-22 11:59:37 +0000467 to SIMD and floating-point functionality from the Secure world is disabled by
468 default and controlled with ENABLE_SVE_FOR_SWD.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100469 This is to avoid corruption of the Non-secure world data in the Z-registers
470 which are aliased by the SIMD and FP registers. The build option is not
471 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000472 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS``
473 enabled. This flag can take the values 0 to 2, to align with the
474 ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be
475 used on systems that have SPM_MM enabled. The default is 1.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100476
Max Shvetsovc4502772021-03-22 11:59:37 +0000477- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
478 SVE is an optional architectural feature for AArch64. Note that this option
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000479 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is
480 automatically disabled when the target architecture is AArch32.
Max Shvetsovc4502772021-03-22 11:59:37 +0000481
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100482- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
483 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
484 default value is set to "none". "strong" is the recommended stack protection
485 level if this feature is desired. "none" disables the stack protection. For
486 all values other than "none", the ``plat_get_stack_protector_canary()``
487 platform hook needs to be implemented. The value is passed as the last
488 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
489
Sumit Gargc0c369c2019-11-15 18:47:53 +0530490- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This
Manish Pandey34a305e2021-10-21 21:53:49 +0100491 flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530492
493- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload.
Manish Pandey34a305e2021-10-21 21:53:49 +0100494 This flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530495
496- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could
497 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends
Manish Pandey34a305e2021-10-21 21:53:49 +0100498 on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530499
500- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector
501 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT``
Manish Pandey34a305e2021-10-21 21:53:49 +0100502 build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530503
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100504- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
505 deprecated platform APIs, helper functions or drivers within Trusted
506 Firmware as error. It can take the value 1 (flag the use of deprecated
507 APIs as error) or 0. The default is 0.
508
509- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
510 targeted at EL3. When set ``0`` (default), no exceptions are expected or
Raghu Krishnamurthy669bf402022-07-25 14:44:33 -0700511 handled at EL3, and a panic will result. The exception to this rule is when
512 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions
513 occuring during normal world execution, are trapped to EL3. Any exception
514 trapped during secure world execution are trapped to the SPMC. This is
515 supported only for AArch64 builds.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100516
Javier Almansa Sobrino0d1f6b12020-09-18 16:47:07 +0100517- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when
518 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``.
519 Default value is 40 (LOG_LEVEL_INFO).
520
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100521- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
522 injection from lower ELs, and this build option enables lower ELs to use
523 Error Records accessed via System Registers to inject faults. This is
524 applicable only to AArch64 builds.
525
526 This feature is intended for testing purposes only, and is advisable to keep
527 disabled for production images.
528
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000529- ``FEATURE_DETECTION``: Boolean option to enable the architectural features
530 detection mechanism. It detects whether the Architectural features enabled
531 through feature specific build flags are supported by the PE or not by
532 validating them either at boot phase or at runtime based on the value
533 possessed by the feature flag (0 to 2) and report error messages at an early
Boyan Karatoteva3e1b072023-06-09 13:22:16 +0100534 stage. This flag will also enable errata ordering checking for ``DEBUG``
535 builds.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000536
537 This prevents and benefits us from EL3 runtime exceptions during context save
538 and restore routines guarded by these build flags. Henceforth validating them
539 before their usage provides more control on the actions taken under them.
540
541 The mechanism permits the build flags to take values 0, 1 or 2 and
542 evaluates them accordingly.
543
544 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example:
545
546 ::
547
548 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time.
549 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime.
550 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime.
551
552 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to
553 0, feature is disabled statically during compilation. If it is defined as 1,
554 feature is validated, wherein FEAT_HCX is detected at boot time. In case not
555 implemented by the PE, a hard panic is generated. Finally, if the flag is set
556 to 2, feature is validated at runtime.
557
558 Note that the entire implementation is divided into two phases, wherein as
559 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not
560 supported and is planned to be handled explicilty in phase-2 implementation.
561
562 FEATURE_DETECTION macro is disabled by default, and is currently an
563 experimental procedure. Platforms can explicitly make use of this by
564 mechanism, by enabling it to validate whether they have set their build flags
565 properly at an early phase.
566
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100567- ``FIP_NAME``: This is an optional build option which specifies the FIP
568 filename for the ``fip`` target. Default is ``fip.bin``.
569
570- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
571 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
572
Sumit Gargc0c369c2019-11-15 18:47:53 +0530573- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values:
574
575 ::
576
577 0: Encryption is done with Secret Symmetric Key (SSK) which is common
578 for a class of devices.
579 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is
580 unique per device.
581
Manish Pandey34a305e2021-10-21 21:53:49 +0100582 This flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530583
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100584- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
585 tool to create certificates as per the Chain of Trust described in
586 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
587 include the certificates in the FIP and FWU_FIP. Default value is '0'.
588
589 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
590 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
591 the corresponding certificates, and to include those certificates in the
592 FIP and FWU_FIP.
593
594 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
595 images will not include support for Trusted Board Boot. The FIP will still
596 include the corresponding certificates. This FIP can be used to verify the
597 Chain of Trust on the host machine through other mechanisms.
598
599 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
600 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
601 will not include the corresponding certificates, causing a boot failure.
602
603- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
604 inherent support for specific EL3 type interrupts. Setting this build option
605 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -0500606 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and
607 :ref:`Interrupt Management Framework<Interrupt Management Framework>`.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100608 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
609 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
610 the Secure Payload interrupts needs to be synchronously handed over to Secure
611 EL1 for handling. The default value of this option is ``0``, which means the
612 Group 0 interrupts are assumed to be handled by Secure EL1.
613
Manish Pandey0e3379d2022-10-10 11:43:08 +0100614- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError
615 Interrupts, resulting from errors in NS world, will be always trapped in
616 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions
617 will be trapped in the current exception level (or in EL1 if the current
618 exception level is EL0).
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100619
620- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
621 software operations are required for CPUs to enter and exit coherency.
622 However, newer systems exist where CPUs' entry to and exit from coherency
623 is managed in hardware. Such systems require software to only initiate these
624 operations, and the rest is managed in hardware, minimizing active software
625 management. In such systems, this boolean option enables TF-A to carry out
626 build and run-time optimizations during boot and power management operations.
627 This option defaults to 0 and if it is enabled, then it implies
628 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
629
630 If this flag is disabled while the platform which TF-A is compiled for
631 includes cores that manage coherency in hardware, then a compilation error is
632 generated. This is based on the fact that a system cannot have, at the same
633 time, cores that manage coherency in hardware and cores that don't. In other
634 words, a platform cannot have, at the same time, cores that require
635 ``HW_ASSISTED_COHERENCY=1`` and cores that require
636 ``HW_ASSISTED_COHERENCY=0``.
637
638 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
639 translation library (xlat tables v2) must be used; version 1 of translation
640 library is not supported.
641
Varun Wadekar0a46eb12023-04-13 21:06:18 +0100642- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for
643 implementation defined system register accesses from lower ELs. Default
644 value is ``0``.
645
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000646- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000647 bottom, higher addresses at the top. This build flag can be set to '1' to
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000648 invert this behavior. Lower addresses will be printed at the top and higher
649 addresses at the bottom.
650
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100651- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
652 used for generating the PKCS keys and subsequent signing of the certificate.
Lionel Debievefefeffb2022-11-14 11:03:42 +0100653 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular``
654 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1
655 RSA 1.5 algorithm which is not TBBR compliant and is retained only for
656 compatibility. The default value of this flag is ``rsa`` which is the TBBR
657 compliant PKCS#1 RSA 2.1 scheme.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100658
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300659- ``KEY_SIZE``: This build flag enables the user to select the key size for
660 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
661 depend on the chosen algorithm and the cryptographic module.
662
Lionel Debievefefeffb2022-11-14 11:03:42 +0100663 +---------------------------+------------------------------------+
664 | KEY_ALG | Possible key sizes |
665 +===========================+====================================+
666 | rsa | 1024 , 2048 (default), 3072, 4096* |
667 +---------------------------+------------------------------------+
668 | ecdsa | unavailable |
669 +---------------------------+------------------------------------+
670 | ecdsa-brainpool-regular | unavailable |
671 +---------------------------+------------------------------------+
672 | ecdsa-brainpool-twisted | unavailable |
673 +---------------------------+------------------------------------+
674
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300675
676 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1.
677 Only 3072 bits size is available with CryptoCell 712 SBROM release 2.
678
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100679- ``HASH_ALG``: This build flag enables the user to select the secure hash
680 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
681 The default value of this flag is ``sha256``.
682
683- ``LDFLAGS``: Extra user options appended to the linkers' command line in
684 addition to the one set by the build system.
685
686- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
687 output compiled into the build. This should be one of the following:
688
689 ::
690
691 0 (LOG_LEVEL_NONE)
692 10 (LOG_LEVEL_ERROR)
693 20 (LOG_LEVEL_NOTICE)
694 30 (LOG_LEVEL_WARNING)
695 40 (LOG_LEVEL_INFO)
696 50 (LOG_LEVEL_VERBOSE)
697
698 All log output up to and including the selected log level is compiled into
699 the build. The default value is 40 in debug builds and 20 in release builds.
700
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000701- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
Manish V Badarkhe92de80a2021-12-16 10:41:47 +0000702 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to
703 provide trust that the code taking the measurements and recording them has
704 not been tampered with.
Sandrine Bailleux533d8b32021-06-10 11:18:04 +0200705
Manish Pandey34a305e2021-10-21 21:53:49 +0100706 This option defaults to 0.
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000707
Manish V Badarkhe8564f772022-02-14 18:31:16 +0000708- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust
709 for Measurement (DRTM). This feature has trust dependency on BL31 for taking
710 the measurements and recording them as per `PSA DRTM specification`_. For
711 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can
712 be used and for the platforms which use ``RESET_TO_BL31`` platform owners
Manish V Badarkhebbe1e422023-02-20 22:44:03 +0000713 should have mechanism to authenticate BL31. This is an experimental feature.
Manish V Badarkhe8564f772022-02-14 18:31:16 +0000714
715 This option defaults to 0.
716
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100717- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
718 specifies the file that contains the Non-Trusted World private key in PEM
719 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
720
721- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
722 optional. It is only needed if the platform makefile specifies that it
723 is required in order to build the ``fwu_fip`` target.
724
725- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
726 contents upon world switch. It can take either 0 (don't save and restore) or
727 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
728 wants the timer registers to be saved and restored.
729
730- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
731 for the BL image. It can be either 0 (include) or 1 (remove). The default
732 value is 0.
733
734- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
735 the underlying hardware is not a full PL011 UART but a minimally compliant
736 generic UART, which is a subset of the PL011. The driver will not access
737 any register that is not part of the SBSA generic UART specification.
738 Default value is 0 (a full PL011 compliant UART is present).
739
740- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
741 must be subdirectory of any depth under ``plat/``, and must contain a
742 platform makefile named ``platform.mk``. For example, to build TF-A for the
743 Arm Juno board, select PLAT=juno.
744
745- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
746 instead of the normal boot flow. When defined, it must specify the entry
747 point address for the preloaded BL33 image. This option is incompatible with
748 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
749 over ``PRELOADED_BL33_BASE``.
750
751- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
752 vector address can be programmed or is fixed on the platform. It can take
753 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
754 programmable reset address, it is expected that a CPU will start executing
755 code directly at the right address, both on a cold and warm reset. In this
756 case, there is no need to identify the entrypoint on boot and the boot path
757 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
758 does not need to be implemented in this case.
759
760- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
761 possible for the PSCI power-state parameter: original and extended State-ID
762 formats. This flag if set to 1, configures the generic PSCI layer to use the
763 extended format. The default value of this flag is 0, which means by default
764 the original power-state format is used by the PSCI implementation. This flag
765 should be specified by the platform makefile and it governs the return value
766 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
767 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
768 set to 1 as well.
769
Wing Li1e9b68a2023-01-26 18:33:36 -0800770- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI
771 OS-initiated mode. This option defaults to 0.
772
Manish Pandeyd419e222023-02-13 12:39:17 +0000773- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100774 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000775 or later CPUs. This flag can take the values 0 to 2, to align with the
776 ``FEATURE_DETECTION`` mechanism.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100777
Manish Pandeyd419e222023-02-13 12:39:17 +0000778- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors
779 originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``,
780 ``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100781
782- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
783 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
784 entrypoint) or 1 (CPU reset to BL31 entrypoint).
785 The default value is 0.
786
787- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
788 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
789 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
790 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
791
792- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
Max Shvetsov06dba292019-12-06 11:50:12 +0000793 file that contains the ROT private key in PEM format and enforces public key
794 hash generation. If ``SAVE_KEYS=1``, this
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100795 file name will be used to save the key.
796
797- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
798 certificate generation tool to save the keys used to establish the Chain of
799 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
800
801- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
802 If a SCP_BL2 image is present then this option must be passed for the ``fip``
803 target.
804
805- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
806 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
807 this file name will be used to save the key.
808
809- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
810 optional. It is only needed if the platform makefile specifies that it
811 is required in order to build the ``fwu_fip`` target.
812
813- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
814 Delegated Exception Interface to BL31 image. This defaults to ``0``.
815
816 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
817 set to ``1``.
818
819- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
820 isolated on separate memory pages. This is a trade-off between security and
821 memory usage. See "Isolating code and read-only data on separate memory
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100822 pages" section in :ref:`Firmware Design`. This flag is disabled by default
823 and affects all BL images.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100824
Samuel Holland31a14e12018-10-17 21:40:18 -0500825- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
826 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
827 allocated in RAM discontiguous from the loaded firmware image. When set, the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000828 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and
Samuel Holland31a14e12018-10-17 21:40:18 -0500829 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
830 sections are placed in RAM immediately following the loaded firmware image.
831
Jiafei Pan0824b452022-02-24 10:47:33 +0800832- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the
833 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM
834 discontiguous from loaded firmware images. When set, the platform need to
835 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This
836 flag is disabled by default and NOLOAD sections are placed in RAM immediately
837 following the loaded firmware image.
838
Jeremy Linton684a0792021-01-26 22:42:03 -0600839- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration
840 access requests via a standard SMCCC defined in `DEN0115`_. When combined with
841 UEFI+ACPI this can provide a certain amount of OS forward compatibility
842 with newer platforms that aren't ECAM compliant.
843
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100844- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
845 This build option is only valid if ``ARCH=aarch64``. The value should be
846 the path to the directory containing the SPD source, relative to
847 ``services/spd/``; the directory is expected to contain a makefile called
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100848 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in
849 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher
850 cannot be enabled when the ``SPM_MM`` option is enabled.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100851
852- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
853 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
854 execution in BL1 just before handing over to BL31. At this point, all
855 firmware images have been loaded in memory, and the MMU and caches are
856 turned off. Refer to the "Debugging options" section for more details.
857
Marc Bonniciabaac162021-12-01 18:00:40 +0000858- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM
859 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
860 component runs at the EL3 exception level. The default value is ``0`` (
861 disabled). This configuration supports pre-Armv8.4 platforms (aka not
862 implementing the ``FEAT_SEL2`` extension). This is an experimental feature.
863
Jens Wiklanderba0ed3e2022-12-14 17:02:16 +0100864- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM
865 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to
866 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading
867 mechanism should be used.
868
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000869- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100870 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
Marc Bonniciabaac162021-12-01 18:00:40 +0000871 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2``
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100872 extension. This is the default when enabling the SPM Dispatcher. When
873 disabled (0) it indicates the SPMC component runs at the S-EL1 execution
Marc Bonniciabaac162021-12-01 18:00:40 +0000874 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations
875 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2``
876 extension).
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100877
Paul Beesleyfe975b42019-09-16 11:29:03 +0000878- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100879 Partition Manager (SPM) implementation. The default value is ``0``
880 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is
881 enabled (``SPD=spmd``).
Paul Beesleyfe975b42019-09-16 11:29:03 +0000882
Manish Pandey3f90ad72020-01-14 11:52:05 +0000883- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100884 description of secure partitions. The build system will parse this file and
885 package all secure partition blobs into the FIP. This file is not
886 necessarily part of TF-A tree. Only available when ``SPD=spmd``.
Manish Pandey3f90ad72020-01-14 11:52:05 +0000887
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100888- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
889 secure interrupts (caught through the FIQ line). Platforms can enable
890 this directive if they need to handle such interruption. When enabled,
891 the FIQ are handled in monitor mode and non secure world is not allowed
892 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
893 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
894
Mark Brown64869972022-04-20 18:14:32 +0100895- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3.
896 Platforms can configure this if they need to lower the hardware
897 limit, for example due to asymmetric configuration or limitations of
898 software run at lower ELs. The default is the architectural maximum
899 of 2048 which should be suitable for most configurations, the
900 hardware will limit the effective VL to the maximum physically supported
901 VL.
902
Jayanth Dodderi Chidanand7c7faff2022-10-11 17:16:07 +0100903- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True
904 Random Number Generator Interface to BL31 image. This defaults to ``0``.
905
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100906- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
907 Boot feature. When set to '1', BL1 and BL2 images include support to load
908 and verify the certificates and images in a FIP, and BL1 includes support
909 for the Firmware Update. The default value is '0'. Generation and inclusion
910 of certificates in the FIP and FWU_FIP depends upon the value of the
911 ``GENERATE_COT`` option.
912
913 .. warning::
914 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
915 already exist in disk, they will be overwritten without further notice.
916
917- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
918 specifies the file that contains the Trusted World private key in PEM
919 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
920
921- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
922 synchronous, (see "Initializing a BL32 Image" section in
923 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
924 synchronous method) or 1 (BL32 is initialized using asynchronous method).
925 Default is 0.
926
927- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
928 routing model which routes non-secure interrupts asynchronously from TSP
929 to EL3 causing immediate preemption of TSP. The EL3 is responsible
930 for saving and restoring the TSP context in this routing model. The
931 default routing model (when the value is 0) is to route non-secure
932 interrupts to TSP allowing it to save its context and hand over
933 synchronously to EL3 via an SMC.
934
935 .. note::
936 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
937 must also be set to ``1``.
938
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100939- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of
940 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set
941 this delay. It can take values in the range (0-15). Default value is ``0``
942 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed.
943 Platforms need to explicitly update this value based on their requirements.
944
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100945- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
946 linker. When the ``LINKER`` build variable points to the armlink linker,
947 this flag is enabled automatically. To enable support for armlink, platforms
948 will have to provide a scatter file for the BL image. Currently, Tegra
949 platforms use the armlink support to compile BL3-1 images.
950
951- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
952 memory region in the BL memory map or not (see "Use of Coherent memory in
953 TF-A" section in :ref:`Firmware Design`). It can take the value 1
954 (Coherent memory region is included) or 0 (Coherent memory region is
955 excluded). Default is 1.
956
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100957- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature
958 exposing a virtual filesystem interface through BL31 as a SiP SMC function.
959 Default is 0.
960
Louis Mayencourt6b232d92020-02-28 16:57:30 +0000961- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
962 firmware configuration framework. This will move the io_policies into a
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100963 configuration device tree, instead of static structure in the code base.
964
Manish V Badarkhead339892020-06-29 10:32:53 +0100965- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors
966 at runtime using fconf. If this flag is enabled, COT descriptors are
967 statically captured in tb_fw_config file in the form of device tree nodes
968 and properties. Currently, COT descriptors used by BL2 are moved to the
969 device tree and COT descriptors used by BL1 are retained in the code
Manish Pandey34a305e2021-10-21 21:53:49 +0100970 base statically.
Manish V Badarkhead339892020-06-29 10:32:53 +0100971
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100972- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in
973 runtime using firmware configuration framework. The platform specific SDEI
974 shared and private events configuration is retrieved from device tree rather
Manish Pandey34a305e2021-10-21 21:53:49 +0100975 than static C structures at compile time. This is only supported if
976 SDEI_SUPPORT build flag is enabled.
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100977
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500978- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0
979 and Group1 secure interrupts using the firmware configuration framework. The
980 platform specific secure interrupt property descriptor is retrieved from
981 device tree in runtime rather than depending on static C structure at compile
Manish Pandey34a305e2021-10-21 21:53:49 +0100982 time.
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500983
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100984- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
985 This feature creates a library of functions to be placed in ROM and thus
986 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default
987 is 0.
988
989- ``V``: Verbose build. If assigned anything other than 0, the build commands
990 are printed. Default is 0.
991
992- ``VERSION_STRING``: String used in the log output for each TF-A image.
993 Defaults to a string formed by concatenating the version number, build type
994 and build string.
995
996- ``W``: Warning level. Some compiler warning options of interest have been
997 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
998 each level enabling more warning options. Default is 0.
999
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +00001000 This option is closely related to the ``E`` option, which enables
1001 ``-Werror``.
1002
1003 - ``W=0`` (default)
1004
1005 Enables a wide assortment of warnings, most notably ``-Wall`` and
1006 ``-Wextra``, as well as various bad practices and things that are likely to
1007 result in errors. Includes some compiler specific flags. No warnings are
1008 expected at this level for any build.
1009
1010 - ``W=1``
1011
1012 Enables warnings we want the generic build to include but are too time
1013 consuming to fix at the moment. It re-enables warnings taken out for
1014 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected
1015 to eventually be merged into ``W=0``. Some warnings are expected on some
1016 builds, but new contributions should not introduce new ones.
1017
1018 - ``W=2`` (recommended)
1019
1020 Enables warnings we want the generic build to include but cannot be enabled
1021 due to external libraries. This level is expected to eventually be merged
1022 into ``W=0``. Lots of warnings are expected, primarily from external
1023 libraries like zlib and compiler-rt, but new controbutions should not
1024 introduce new ones.
1025
1026 - ``W=3``
1027
1028 Enables warnings that are informative but not necessary and generally too
1029 verbose and frequently ignored. A very large number of warnings are
1030 expected.
1031
1032 The exact set of warning flags depends on the compiler and TF-A warning
1033 level, however they are all succinctly set in the top-level Makefile. Please
1034 refer to the `GCC`_ or `Clang`_ documentation for more information on the
1035 individual flags.
1036
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001037- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
1038 the CPU after warm boot. This is applicable for platforms which do not
1039 require interconnect programming to enable cache coherency (eg: single
1040 cluster platforms). If this option is enabled, then warm boot path
1041 enables D-caches immediately after enabling MMU. This option defaults to 0.
1042
Manish V Badarkhe75c972a2020-03-22 05:06:38 +00001043- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
1044 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
1045 default value of this flag is ``no``. Note this option must be enabled only
1046 for ARM architecture greater than Armv8.5-A.
1047
Manish V Badarkhea59fa012020-07-31 08:38:49 +01001048- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
1049 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
1050 The default value of this flag is ``0``.
1051
1052 ``AT`` speculative errata workaround disables stage1 page table walk for
1053 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point
1054 produces either the correct result or failure without TLB allocation.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +01001055
1056 This boolean option enables errata for all below CPUs.
1057
Manish V Badarkhea59fa012020-07-31 08:38:49 +01001058 +---------+--------------+-------------------------+
1059 | Errata | CPU | Workaround Define |
1060 +=========+==============+=========================+
1061 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` |
1062 +---------+--------------+-------------------------+
1063 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` |
1064 +---------+--------------+-------------------------+
1065 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` |
1066 +---------+--------------+-------------------------+
1067 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` |
1068 +---------+--------------+-------------------------+
1069 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` |
1070 +---------+--------------+-------------------------+
1071
1072 .. note::
1073 This option is enabled by build only if platform sets any of above defines
1074 mentioned in ’Workaround Define' column in the table.
1075 If this option is enabled for the EL3 software then EL2 software also must
1076 implement this workaround due to the behaviour of the errata mentioned
1077 in new SDEN document which will get published soon.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +01001078
Manish Pandey7c6fcb42022-09-27 14:30:34 +01001079- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR
Varun Wadekar92234852020-06-12 10:11:28 -07001080 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
1081 This flag is disabled by default.
1082
Juan Pablo Conde52865522022-06-28 16:56:32 -04001083- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the
1084 host machine where a custom installation of OpenSSL is located, which is used
1085 to build the certificate generation, firmware encryption and FIP tools. If
1086 this option is not set, the default OS installation will be used.
Manish V Badarkhe3589b702020-07-29 10:58:44 +01001087
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -05001088- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for
1089 functions that wait for an arbitrary time length (udelay and mdelay). The
1090 default value is 0.
1091
Jayanth Dodderi Chidanand69316752022-05-09 12:33:03 +01001092- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record
1093 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an
1094 optional architectural feature for AArch64. This flag can take the values
1095 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0
1096 and it is automatically disabled when the target architecture is AArch32.
johpow0181865962022-01-28 17:06:20 -06001097
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001098- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer
Manish V Badarkhe20df29c2021-07-02 09:10:56 +01001099 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented
1100 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001101 feature for AArch64. This flag can take the values 0 to 2, to align with the
1102 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically
1103 disabled when the target architecture is AArch32.
Manish V Badarkhe20df29c2021-07-02 09:10:56 +01001104
Andre Przywara44e33e02022-11-17 16:42:09 +00001105- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system
Manish V Badarkhef356f7e2021-06-29 11:44:20 +01001106 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented
1107 but unused). This feature is available if trace unit such as ETMv4.x, and
Andre Przywara44e33e02022-11-17 16:42:09 +00001108 ETE(extending ETM feature) is implemented. This flag can take the values
1109 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0.
Manish V Badarkhef356f7e2021-06-29 11:44:20 +01001110
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +00001111- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers
Manish V Badarkhe51a97112021-07-08 09:33:18 +01001112 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused),
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +00001113 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align
1114 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default.
Manish V Badarkhe51a97112021-07-08 09:33:18 +01001115
Tamas Banc9ccc272022-01-18 16:20:47 +01001116- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA
1117 APIs on platforms that doesn't support RSS (providing Arm CCA HES
1118 functionalities). When enabled (``1``), a mocked version of the APIs are used.
1119 The default value is 0.
1120
Okash Khawaja037b56e2022-11-04 12:38:01 +00001121- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine
1122 ``plat_can_cmo`` which will return zero if cache management operations should
1123 be skipped and non-zero otherwise. By default, this option is disabled which
1124 means platform hook won't be checked and CMOs will always be performed when
1125 related functions are called.
1126
Sona Mathew6315c582023-03-15 09:40:36 -05001127- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management
1128 firmware interface for the BL31 image. By default its disabled (``0``).
1129
1130- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the
1131 errata mitigation for platforms with a non-arm interconnect using the errata
1132 ABI. By default its disabled (``0``).
1133
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001134GICv3 driver options
1135--------------------
1136
1137GICv3 driver files are included using directive:
1138
1139``include drivers/arm/gic/v3/gicv3.mk``
1140
1141The driver can be configured with the following options set in the platform
1142makefile:
1143
Andre Przywarae1cc1302020-03-25 15:50:38 +00001144- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3.
1145 Enabling this option will add runtime detection support for the
1146 GIC-600, so is safe to select even for a GIC500 implementation.
1147 This option defaults to 0.
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001148
Varun Wadekareea6dc12021-05-04 16:14:09 -07001149- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit
1150 for GIC-600 AE. Enabling this option will introduce support to initialize
1151 the FMU. Platforms should call the init function during boot to enable the
1152 FMU and its safety mechanisms. This option defaults to 0.
1153
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001154- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip
1155 functionality. This option defaults to 0
1156
1157- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation
1158 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore``
1159 functions. This is required for FVP platform which need to simulate GIC save
1160 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.
1161
Alexei Fedorov19705932020-04-06 19:00:35 +01001162- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver.
1163 This option defaults to 0.
1164
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001165- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended
1166 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.
1167
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001168Debugging options
1169-----------------
1170
1171To compile a debug version and make the build more verbose use
1172
1173.. code:: shell
1174
1175 make PLAT=<platform> DEBUG=1 V=1 all
1176
Daniel Boulbydf83a832022-05-03 16:46:16 +01001177AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools
1178(for example Arm-DS) might not support this and may need an older version of
1179DWARF symbols to be emitted by GCC. This can be achieved by using the
1180``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting
1181the version to 4 is recommended for Arm-DS.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001182
1183When debugging logic problems it might also be useful to disable all compiler
1184optimizations by using ``-O0``.
1185
1186.. warning::
1187 Using ``-O0`` could cause output images to be larger and base addresses
1188 might need to be recalculated (see the **Memory layout on Arm development
1189 platforms** section in the :ref:`Firmware Design`).
1190
1191Extra debug options can be passed to the build system by setting ``CFLAGS`` or
1192``LDFLAGS``:
1193
1194.. code:: shell
1195
1196 CFLAGS='-O0 -gdwarf-2' \
1197 make PLAT=<platform> DEBUG=1 V=1 all
1198
1199Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
1200ignored as the linker is called directly.
1201
1202It is also possible to introduce an infinite loop to help in debugging the
1203post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
1204``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common`
1205section. In this case, the developer may take control of the target using a
Daniel Boulbydf83a832022-05-03 16:46:16 +01001206debugger when indicated by the console output. When using Arm-DS, the following
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001207commands can be used:
1208
1209::
1210
1211 # Stop target execution
1212 interrupt
1213
1214 #
1215 # Prepare your debugging environment, e.g. set breakpoints
1216 #
1217
1218 # Jump over the debug loop
1219 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1220
1221 # Resume execution
1222 continue
1223
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001224Firmware update options
1225-----------------------
1226
1227- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used
1228 in defining the firmware update metadata structure. This flag is by default
1229 set to '2'.
1230
1231- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each
1232 firmware bank. Each firmware bank must have the same number of images as per
1233 the `PSA FW update specification`_.
1234 This flag is used in defining the firmware update metadata structure. This
1235 flag is by default set to '1'.
1236
Manish V Badarkheda87af12021-06-20 21:14:46 +01001237- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the
1238 `PSA FW update specification`_. The default value is 0, and this is an
1239 experimental feature.
1240 PSA firmware update implementation has some limitations, such as BL2 is
1241 not part of the protocol-updatable images, if BL2 needs to be updated, then
1242 it should be done through another platform-defined mechanism, and it assumes
1243 that the platform's hardware supports CRC32 instructions.
1244
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001245--------------
1246
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06001247*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
Jeremy Linton684a0792021-01-26 22:42:03 -06001248
1249.. _DEN0115: https://developer.arm.com/docs/den0115/latest
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001250.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
Manish V Badarkhe8564f772022-02-14 18:31:16 +00001251.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +00001252.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html
1253.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html