| developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEBUG_H |
| 8 | #define PLATFORM_DEBUG_H |
| 9 | |
| 10 | #define sync_writel(addr, val) \ |
| 11 | do { mmio_write_32((addr), (val)); dsbsy(); } while (0) |
| 12 | |
| 13 | #define MCU_BIU_BASE 0x0c530000 |
| 14 | #define MISC1_CFG_BASE 0xb00 |
| 15 | #define CA15M_CFG_BASE 0x2000 |
| 16 | #define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00) |
| 17 | #define CA15M_DBG_CONTROL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x728) |
| 18 | #define CA15M_PWR_RST_CTL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x08) |
| 19 | #define VPROC_EXT_CTL 0x10006290 |
| 20 | |
| 21 | #define CFG_SF_CTRL 0x0c510014 |
| 22 | #define CFG_SF_INI 0x0c510010 |
| 23 | |
| 24 | #define BIT_CA15M_L2PARITY_EN (1 << 1) |
| 25 | #define BIT_CA15M_LASTPC_DIS (1 << 8) |
| 26 | |
| 27 | #define MP1_CPUTOP_PWR_CON 0x10006218 |
| 28 | |
| 29 | #define MCU_ALL_PWR_ON_CTRL 0x0c530b58 |
| 30 | #define PLAT_MTK_CIRCULAR_BUFFER_UNLOCK 0xefab4133 |
| 31 | #define PLAT_MTK_CIRCULAR_BUFFER_LOCK 0xefab4134 |
| 32 | |
| 33 | extern void circular_buffer_setup(void); |
| 34 | extern void l2c_parity_check_setup(void); |
| 35 | extern void clear_all_on_mux(void); |
| 36 | #endif /* PLATFORM_DEBUG_H */ |