| Haojian Zhuang | 5f281b3 | 2017-05-24 08:45:05 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef HI6220_REGS_PERI_H |
| 8 | #define HI6220_REGS_PERI_H |
| Haojian Zhuang | 5f281b3 | 2017-05-24 08:45:05 +0800 | [diff] [blame] | 9 | |
| 10 | #define PERI_BASE 0xF7030000 |
| 11 | |
| 12 | #define PERI_SC_PERIPH_CTRL1 (PERI_BASE + 0x000) |
| 13 | #define PERI_SC_PERIPH_CTRL2 (PERI_BASE + 0x004) |
| 14 | #define PERI_SC_PERIPH_CTRL3 (PERI_BASE + 0x008) |
| 15 | #define PERI_SC_PERIPH_CTRL4 (PERI_BASE + 0x00c) |
| 16 | #define PERI_SC_PERIPH_CTRL5 (PERI_BASE + 0x010) |
| 17 | #define PERI_SC_PERIPH_CTRL6 (PERI_BASE + 0x014) |
| 18 | #define PERI_SC_PERIPH_CTRL8 (PERI_BASE + 0x018) |
| 19 | #define PERI_SC_PERIPH_CTRL9 (PERI_BASE + 0x01c) |
| 20 | #define PERI_SC_PERIPH_CTRL10 (PERI_BASE + 0x020) |
| 21 | #define PERI_SC_PERIPH_CTRL12 (PERI_BASE + 0x024) |
| 22 | #define PERI_SC_PERIPH_CTRL13 (PERI_BASE + 0x028) |
| 23 | #define PERI_SC_PERIPH_CTRL14 (PERI_BASE + 0x02c) |
| 24 | |
| 25 | #define PERI_SC_DDR_CTRL0 (PERI_BASE + 0x050) |
| 26 | #define PERI_SC_PERIPH_STAT1 (PERI_BASE + 0x094) |
| 27 | |
| 28 | #define PERI_SC_PERIPH_CLKEN0 (PERI_BASE + 0x200) |
| 29 | #define PERI_SC_PERIPH_CLKDIS0 (PERI_BASE + 0x204) |
| 30 | #define PERI_SC_PERIPH_CLKSTAT0 (PERI_BASE + 0x208) |
| 31 | #define PERI_SC_PERIPH_CLKEN1 (PERI_BASE + 0x210) |
| 32 | #define PERI_SC_PERIPH_CLKDIS1 (PERI_BASE + 0x214) |
| 33 | #define PERI_SC_PERIPH_CLKSTAT1 (PERI_BASE + 0x218) |
| 34 | #define PERI_SC_PERIPH_CLKEN2 (PERI_BASE + 0x220) |
| 35 | #define PERI_SC_PERIPH_CLKDIS2 (PERI_BASE + 0x224) |
| 36 | #define PERI_SC_PERIPH_CLKSTAT2 (PERI_BASE + 0x228) |
| 37 | #define PERI_SC_PERIPH_CLKEN3 (PERI_BASE + 0x230) |
| 38 | #define PERI_SC_PERIPH_CLKDIS3 (PERI_BASE + 0x234) |
| 39 | #define PERI_SC_PERIPH_CLKSTAT3 (PERI_BASE + 0x238) |
| 40 | #define PERI_SC_PERIPH_CLKEN8 (PERI_BASE + 0x240) |
| 41 | #define PERI_SC_PERIPH_CLKDIS8 (PERI_BASE + 0x244) |
| 42 | #define PERI_SC_PERIPH_CLKSTAT8 (PERI_BASE + 0x248) |
| 43 | #define PERI_SC_PERIPH_CLKEN9 (PERI_BASE + 0x250) |
| 44 | #define PERI_SC_PERIPH_CLKDIS9 (PERI_BASE + 0x254) |
| 45 | #define PERI_SC_PERIPH_CLKSTAT9 (PERI_BASE + 0x258) |
| 46 | #define PERI_SC_PERIPH_CLKEN10 (PERI_BASE + 0x260) |
| 47 | #define PERI_SC_PERIPH_CLKDIS10 (PERI_BASE + 0x264) |
| 48 | #define PERI_SC_PERIPH_CLKSTAT10 (PERI_BASE + 0x268) |
| 49 | #define PERI_SC_PERIPH_CLKEN12 (PERI_BASE + 0x270) |
| 50 | #define PERI_SC_PERIPH_CLKDIS12 (PERI_BASE + 0x274) |
| 51 | #define PERI_SC_PERIPH_CLKSTAT12 (PERI_BASE + 0x278) |
| 52 | |
| 53 | #define PERI_SC_PERIPH_RSTEN0 (PERI_BASE + 0x300) |
| 54 | #define PERI_SC_PERIPH_RSTDIS0 (PERI_BASE + 0x304) |
| 55 | #define PERI_SC_PERIPH_RSTSTAT0 (PERI_BASE + 0x308) |
| 56 | #define PERI_SC_PERIPH_RSTEN1 (PERI_BASE + 0x310) |
| 57 | #define PERI_SC_PERIPH_RSTDIS1 (PERI_BASE + 0x314) |
| 58 | #define PERI_SC_PERIPH_RSTSTAT1 (PERI_BASE + 0x318) |
| 59 | #define PERI_SC_PERIPH_RSTEN2 (PERI_BASE + 0x320) |
| 60 | #define PERI_SC_PERIPH_RSTDIS2 (PERI_BASE + 0x324) |
| 61 | #define PERI_SC_PERIPH_RSTSTAT2 (PERI_BASE + 0x328) |
| 62 | #define PERI_SC_PERIPH_RSTEN3 (PERI_BASE + 0x330) |
| 63 | #define PERI_SC_PERIPH_RSTDIS3 (PERI_BASE + 0x334) |
| 64 | #define PERI_SC_PERIPH_RSTSTAT3 (PERI_BASE + 0x338) |
| 65 | #define PERI_SC_PERIPH_RSTEN8 (PERI_BASE + 0x340) |
| 66 | #define PERI_SC_PERIPH_RSTDIS8 (PERI_BASE + 0x344) |
| 67 | #define PERI_SC_PERIPH_RSTSTAT8 (PERI_BASE + 0x338) |
| 68 | |
| 69 | #define PERI_SC_CLK_SEL0 (PERI_BASE + 0x400) |
| 70 | #define PERI_SC_CLKCFG8BIT1 (PERI_BASE + 0x494) |
| 71 | #define PERI_SC_CLKCFG8BIT2 (PERI_BASE + 0x498) |
| 72 | #define PERI_SC_RESERVED8_ADDR (PERI_BASE + 0xd04) |
| 73 | |
| 74 | /* PERI_SC_PERIPH_CTRL1 */ |
| 75 | #define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) |
| 76 | #define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) |
| 77 | #define PERI_CTRL1_HIFI_INT_MASK (1 << 1) |
| 78 | #define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2) |
| 79 | #define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16) |
| 80 | #define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17) |
| 81 | #define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18) |
| 82 | |
| 83 | /* PERI_SC_PERIPH_CTRL2 */ |
| 84 | #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0) |
| 85 | #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2) |
| 86 | #define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6) |
| 87 | #define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7) |
| 88 | #define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8) |
| 89 | #define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9) |
| 90 | #define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12) |
| 91 | #define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15) |
| 92 | #define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16) |
| 93 | #define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20) |
| 94 | #define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22) |
| 95 | #define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26) |
| 96 | #define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27) |
| 97 | #define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28) |
| 98 | |
| 99 | /* PERI_SC_PERIPH_CTRL3 */ |
| 100 | #define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0) |
| 101 | #define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12) |
| 102 | #define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13) |
| 103 | #define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14) |
| 104 | #define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16) |
| 105 | #define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18) |
| 106 | #define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20) |
| 107 | #define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22) |
| 108 | #define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24) |
| 109 | |
| 110 | /* PERI_SC_PERIPH_CTRL4 */ |
| 111 | #define PERI_CTRL4_PICO_FSELV (1 << 0) |
| 112 | #define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3) |
| 113 | #define PERI_CTRL4_PICO_REFCLKSEL (1 << 4) |
| 114 | #define PERI_CTRL4_PICO_SIDDQ (1 << 6) |
| 115 | #define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7) |
| 116 | #define PERI_CTRL4_PICO_OGDISABLE (1 << 8) |
| 117 | #define PERI_CTRL4_PICO_COMMONONN (1 << 9) |
| 118 | #define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10) |
| 119 | #define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11) |
| 120 | #define PERI_CTRL4_PICO_VATESTENB (1 << 12) |
| 121 | #define PERI_CTRL4_PICO_SUSPENDM (1 << 14) |
| 122 | #define PERI_CTRL4_PICO_SLEEPM (1 << 15) |
| 123 | #define PERI_CTRL4_BC11_C (1 << 16) |
| 124 | #define PERI_CTRL4_BC11_B (1 << 17) |
| 125 | #define PERI_CTRL4_BC11_A (1 << 18) |
| 126 | #define PERI_CTRL4_BC11_GND (1 << 19) |
| 127 | #define PERI_CTRL4_BC11_FLOAT (1 << 20) |
| 128 | #define PERI_CTRL4_OTG_PHY_SEL (1 << 21) |
| 129 | #define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22) |
| 130 | #define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24) |
| 131 | #define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25) |
| 132 | #define PERI_CTRL4_OTG_IDPULLUP (1 << 26) |
| 133 | #define PERI_CTRL4_OTG_DRVBUS (1 << 27) |
| 134 | #define PERI_CTRL4_OTG_SESSEND (1 << 28) |
| 135 | #define PERI_CTRL4_OTG_BVALID (1 << 29) |
| 136 | #define PERI_CTRL4_OTG_AVALID (1 << 30) |
| Justin Chadwell | 01715f9 | 2019-07-11 09:35:01 +0100 | [diff] [blame] | 137 | #define PERI_CTRL4_OTG_VBUSVALID (1U << 31) |
| Haojian Zhuang | 5f281b3 | 2017-05-24 08:45:05 +0800 | [diff] [blame] | 138 | |
| 139 | /* PERI_SC_PERIPH_CTRL5 */ |
| 140 | #define PERI_CTRL5_USBOTG_RES_SEL (1 << 3) |
| 141 | #define PERI_CTRL5_PICOPHY_ACAENB (1 << 4) |
| 142 | #define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5) |
| 143 | #define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6) |
| 144 | #define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7) |
| 145 | #define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8) |
| 146 | #define PERI_CTRL5_PICOPHY_DCDENB (1 << 9) |
| 147 | #define PERI_CTRL5_PICOPHY_IDDIG (1 << 10) |
| 148 | #define PERI_CTRL5_DBG_MUX (1 << 11) |
| 149 | |
| 150 | /* PERI_SC_PERIPH_CTRL6 */ |
| 151 | #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0) |
| 152 | #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4) |
| 153 | #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6) |
| 154 | #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10) |
| 155 | #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11) |
| 156 | #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12) |
| 157 | |
| 158 | /* PERI_SC_PERIPH_CTRL8 */ |
| 159 | #define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0) |
| 160 | #define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2) |
| 161 | #define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4) |
| 162 | #define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6) |
| 163 | #define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8) |
| 164 | #define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11) |
| 165 | #define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12) |
| 166 | #define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16) |
| 167 | #define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20) |
| 168 | #define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28) |
| 169 | |
| 170 | /* PERI_SC_PERIPH_CTRL9 */ |
| 171 | #define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0) |
| 172 | #define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1) |
| 173 | #define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4) |
| 174 | #define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8) |
| 175 | |
| 176 | /* |
| 177 | * PERI_SC_PERIPH_CLKEN0 |
| 178 | * PERI_SC_PERIPH_CLKDIS0 |
| 179 | * PERI_SC_PERIPH_CLKSTAT0 |
| 180 | */ |
| 181 | #define PERI_CLK0_MMC0 (1 << 0) |
| 182 | #define PERI_CLK0_MMC1 (1 << 1) |
| 183 | #define PERI_CLK0_MMC2 (1 << 2) |
| 184 | #define PERI_CLK0_NANDC (1 << 3) |
| 185 | #define PERI_CLK0_USBOTG (1 << 4) |
| 186 | #define PERI_CLK0_PICOPHY (1 << 5) |
| 187 | #define PERI_CLK0_PLL (1 << 6) |
| 188 | |
| 189 | /* |
| 190 | * PERI_SC_PERIPH_CLKEN1 |
| 191 | * PERI_SC_PERIPH_CLKDIS1 |
| 192 | * PERI_SC_PERIPH_CLKSTAT1 |
| 193 | */ |
| 194 | #define PERI_CLK1_HIFI (1 << 0) |
| 195 | #define PERI_CLK1_DIGACODEC (1 << 5) |
| 196 | |
| 197 | /* |
| 198 | * PERI_SC_PERIPH_CLKEN2 |
| 199 | * PERI_SC_PERIPH_CLKDIS2 |
| 200 | * PERI_SC_PERIPH_CLKSTAT2 |
| 201 | */ |
| 202 | #define PERI_CLK2_IPF (1 << 0) |
| 203 | #define PERI_CLK2_SOCP (1 << 1) |
| 204 | #define PERI_CLK2_DMAC (1 << 2) |
| 205 | #define PERI_CLK2_SECENG (1 << 3) |
| 206 | #define PERI_CLK2_HPM0 (1 << 5) |
| 207 | #define PERI_CLK2_HPM1 (1 << 6) |
| 208 | #define PERI_CLK2_HPM2 (1 << 7) |
| 209 | #define PERI_CLK2_HPM3 (1 << 8) |
| 210 | |
| 211 | /* |
| 212 | * PERI_SC_PERIPH_CLKEN3 |
| 213 | * PERI_SC_PERIPH_CLKDIS3 |
| 214 | * PERI_SC_PERIPH_CLKSTAT3 |
| 215 | */ |
| 216 | #define PERI_CLK3_CSSYS (1 << 0) |
| 217 | #define PERI_CLK3_I2C0 (1 << 1) |
| 218 | #define PERI_CLK3_I2C1 (1 << 2) |
| 219 | #define PERI_CLK3_I2C2 (1 << 3) |
| 220 | #define PERI_CLK3_I2C3 (1 << 4) |
| 221 | #define PERI_CLK3_UART1 (1 << 5) |
| 222 | #define PERI_CLK3_UART2 (1 << 6) |
| 223 | #define PERI_CLK3_UART3 (1 << 7) |
| 224 | #define PERI_CLK3_UART4 (1 << 8) |
| 225 | #define PERI_CLK3_SSP (1 << 9) |
| 226 | #define PERI_CLK3_PWM (1 << 10) |
| 227 | #define PERI_CLK3_BLPWM (1 << 11) |
| 228 | #define PERI_CLK3_TSENSOR (1 << 12) |
| 229 | #define PERI_CLK3_GPS (1 << 15) |
| 230 | #define PERI_CLK3_TCXO_PAD0 (1 << 16) |
| 231 | #define PERI_CLK3_TCXO_PAD1 (1 << 17) |
| 232 | #define PERI_CLK3_DAPB (1 << 18) |
| 233 | #define PERI_CLK3_HKADC (1 << 19) |
| 234 | #define PERI_CLK3_CODEC_SSI (1 << 20) |
| 235 | #define PERI_CLK3_TZPC_DEP (1 << 21) |
| 236 | |
| 237 | /* |
| 238 | * PERI_SC_PERIPH_CLKEN8 |
| 239 | * PERI_SC_PERIPH_CLKDIS8 |
| 240 | * PERI_SC_PERIPH_CLKSTAT8 |
| 241 | */ |
| 242 | #define PERI_CLK8_RS0 (1 << 0) |
| 243 | #define PERI_CLK8_RS2 (1 << 1) |
| 244 | #define PERI_CLK8_RS3 (1 << 2) |
| 245 | #define PERI_CLK8_MS0 (1 << 3) |
| 246 | #define PERI_CLK8_MS2 (1 << 5) |
| 247 | #define PERI_CLK8_XG2RAM0 (1 << 6) |
| 248 | #define PERI_CLK8_X2SRAM (1 << 7) |
| 249 | #define PERI_CLK8_SRAM (1 << 8) |
| 250 | #define PERI_CLK8_ROM (1 << 9) |
| 251 | #define PERI_CLK8_HARQ (1 << 10) |
| 252 | #define PERI_CLK8_MMU (1 << 11) |
| 253 | #define PERI_CLK8_DDRC (1 << 12) |
| 254 | #define PERI_CLK8_DDRPHY (1 << 13) |
| 255 | #define PERI_CLK8_DDRPHY_REF (1 << 14) |
| 256 | #define PERI_CLK8_X2X_SYSNOC (1 << 15) |
| 257 | #define PERI_CLK8_X2X_CCPU (1 << 16) |
| 258 | #define PERI_CLK8_DDRT (1 << 17) |
| 259 | #define PERI_CLK8_DDRPACK_RS (1 << 18) |
| 260 | |
| 261 | /* |
| 262 | * PERI_SC_PERIPH_CLKEN9 |
| 263 | * PERI_SC_PERIPH_CLKDIS9 |
| 264 | * PERI_SC_PERIPH_CLKSTAT9 |
| 265 | */ |
| 266 | #define PERI_CLK9_CARM_DAP (1 << 0) |
| 267 | #define PERI_CLK9_CARM_ATB (1 << 1) |
| 268 | #define PERI_CLK9_CARM_LBUS (1 << 2) |
| 269 | #define PERI_CLK9_CARM_KERNEL (1 << 3) |
| 270 | |
| 271 | /* |
| 272 | * PERI_SC_PERIPH_CLKEN10 |
| 273 | * PERI_SC_PERIPH_CLKDIS10 |
| 274 | * PERI_SC_PERIPH_CLKSTAT10 |
| 275 | */ |
| 276 | #define PERI_CLK10_IPF_CCPU (1 << 0) |
| 277 | #define PERI_CLK10_SOCP_CCPU (1 << 1) |
| 278 | #define PERI_CLK10_SECENG_CCPU (1 << 2) |
| 279 | #define PERI_CLK10_HARQ_CCPU (1 << 3) |
| 280 | #define PERI_CLK10_IPF_MCU (1 << 16) |
| 281 | #define PERI_CLK10_SOCP_MCU (1 << 17) |
| 282 | #define PERI_CLK10_SECENG_MCU (1 << 18) |
| 283 | #define PERI_CLK10_HARQ_MCU (1 << 19) |
| 284 | |
| 285 | /* |
| 286 | * PERI_SC_PERIPH_CLKEN12 |
| 287 | * PERI_SC_PERIPH_CLKDIS12 |
| 288 | * PERI_SC_PERIPH_CLKSTAT12 |
| 289 | */ |
| 290 | #define PERI_CLK12_HIFI_SRC (1 << 0) |
| 291 | #define PERI_CLK12_MMC0_SRC (1 << 1) |
| 292 | #define PERI_CLK12_MMC1_SRC (1 << 2) |
| 293 | #define PERI_CLK12_MMC2_SRC (1 << 3) |
| 294 | #define PERI_CLK12_SYSPLL_DIV (1 << 4) |
| 295 | #define PERI_CLK12_TPIU_SRC (1 << 5) |
| 296 | #define PERI_CLK12_MMC0_HF (1 << 6) |
| 297 | #define PERI_CLK12_MMC1_HF (1 << 7) |
| 298 | #define PERI_CLK12_PLL_TEST_SRC (1 << 8) |
| 299 | #define PERI_CLK12_CODEC_SOC (1 << 9) |
| 300 | #define PERI_CLK12_MEDIA (1 << 10) |
| 301 | |
| 302 | /* |
| 303 | * PERI_SC_PERIPH_RSTEN0 |
| 304 | * PERI_SC_PERIPH_RSTDIS0 |
| 305 | * PERI_SC_PERIPH_RSTSTAT0 |
| 306 | */ |
| 307 | #define PERI_RST0_MMC0 (1 << 0) |
| 308 | #define PERI_RST0_MMC1 (1 << 1) |
| 309 | #define PERI_RST0_MMC2 (1 << 2) |
| 310 | #define PERI_RST0_NANDC (1 << 3) |
| 311 | #define PERI_RST0_USBOTG_BUS (1 << 4) |
| 312 | #define PERI_RST0_POR_PICOPHY (1 << 5) |
| 313 | #define PERI_RST0_USBOTG (1 << 6) |
| 314 | #define PERI_RST0_USBOTG_32K (1 << 7) |
| 315 | |
| 316 | /* |
| 317 | * PERI_SC_PERIPH_RSTEN1 |
| 318 | * PERI_SC_PERIPH_RSTDIS1 |
| 319 | * PERI_SC_PERIPH_RSTSTAT1 |
| 320 | */ |
| 321 | #define PERI_RST1_HIFI (1 << 0) |
| 322 | #define PERI_RST1_DIGACODEC (1 << 5) |
| 323 | |
| 324 | /* |
| 325 | * PERI_SC_PERIPH_RSTEN2 |
| 326 | * PERI_SC_PERIPH_RSTDIS2 |
| 327 | * PERI_SC_PERIPH_RSTSTAT2 |
| 328 | */ |
| 329 | #define PERI_RST2_IPF (1 << 0) |
| 330 | #define PERI_RST2_SOCP (1 << 1) |
| 331 | #define PERI_RST2_DMAC (1 << 2) |
| 332 | #define PERI_RST2_SECENG (1 << 3) |
| 333 | #define PERI_RST2_ABB (1 << 4) |
| 334 | #define PERI_RST2_HPM0 (1 << 5) |
| 335 | #define PERI_RST2_HPM1 (1 << 6) |
| 336 | #define PERI_RST2_HPM2 (1 << 7) |
| 337 | #define PERI_RST2_HPM3 (1 << 8) |
| 338 | |
| 339 | /* |
| 340 | * PERI_SC_PERIPH_RSTEN3 |
| 341 | * PERI_SC_PERIPH_RSTDIS3 |
| 342 | * PERI_SC_PERIPH_RSTSTAT3 |
| 343 | */ |
| 344 | #define PERI_RST3_CSSYS (1 << 0) |
| 345 | #define PERI_RST3_I2C0 (1 << 1) |
| 346 | #define PERI_RST3_I2C1 (1 << 2) |
| 347 | #define PERI_RST3_I2C2 (1 << 3) |
| 348 | #define PERI_RST3_I2C3 (1 << 4) |
| 349 | #define PERI_RST3_UART1 (1 << 5) |
| 350 | #define PERI_RST3_UART2 (1 << 6) |
| 351 | #define PERI_RST3_UART3 (1 << 7) |
| 352 | #define PERI_RST3_UART4 (1 << 8) |
| 353 | #define PERI_RST3_SSP (1 << 9) |
| 354 | #define PERI_RST3_PWM (1 << 10) |
| 355 | #define PERI_RST3_BLPWM (1 << 11) |
| 356 | #define PERI_RST3_TSENSOR (1 << 12) |
| 357 | #define PERI_RST3_DAPB (1 << 18) |
| 358 | #define PERI_RST3_HKADC (1 << 19) |
| 359 | #define PERI_RST3_CODEC (1 << 20) |
| 360 | |
| 361 | /* |
| 362 | * PERI_SC_PERIPH_RSTEN8 |
| 363 | * PERI_SC_PERIPH_RSTDIS8 |
| 364 | * PERI_SC_PERIPH_RSTSTAT8 |
| 365 | */ |
| 366 | #define PERI_RST8_RS0 (1 << 0) |
| 367 | #define PERI_RST8_RS2 (1 << 1) |
| 368 | #define PERI_RST8_RS3 (1 << 2) |
| 369 | #define PERI_RST8_MS0 (1 << 3) |
| 370 | #define PERI_RST8_MS2 (1 << 5) |
| 371 | #define PERI_RST8_XG2RAM0 (1 << 6) |
| 372 | #define PERI_RST8_X2SRAM_TZMA (1 << 7) |
| 373 | #define PERI_RST8_SRAM (1 << 8) |
| 374 | #define PERI_RST8_HARQ (1 << 10) |
| 375 | #define PERI_RST8_DDRC (1 << 12) |
| 376 | #define PERI_RST8_DDRC_APB (1 << 13) |
| 377 | #define PERI_RST8_DDRPACK_APB (1 << 14) |
| 378 | #define PERI_RST8_DDRT (1 << 17) |
| 379 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 380 | #endif /* HI6220_REGS_PERI_H */ |