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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Build Options
2=============
3
4The TF-A build system supports the following build options. Unless mentioned
5otherwise, these options are expected to be specified at the build command
6line and are not to be modified in any component makefiles. Note that the
7build system doesn't track dependency for build options. Therefore, if any of
8the build options are changed from a previous build, a clean build must be
9performed.
10
11.. _build_options_common:
12
13Common build options
14--------------------
15
16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
18 code having a smaller resulting size.
19
20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
22 directory containing the SP source, relative to the ``bl32/``; the directory
23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
24
johpow01fa59c6f2020-10-02 13:41:11 -050025- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return
26 zero at all but the highest implemented exception level. Reads from the
27 memory mapped view are unaffected by this control.
28
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010029- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
31 ``aarch64``.
32
Alexei Fedorov132e6652020-12-07 16:38:53 +000033- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies
34 one or more feature modifiers. This option has the form ``[no]feature+...``
35 and defaults to ``none``. It translates into compiler option
36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the
37 list of supported feature modifiers.
38
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010039- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
42 :ref:`Firmware Design`.
43
44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
47
48- ``BL2``: This is an optional build option which specifies the path to BL2
49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
50 built.
51
52- ``BL2U``: This is an optional build option which specifies the path to
53 BL2U image. In this case, the BL2U in TF-A will not be built.
54
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060055- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset
56 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
57 entrypoint) or 1 (CPU reset to BL2 entrypoint).
58 The default value is 0.
59
60- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3.
61 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be
62 true in a 4-world system where RESET_TO_BL2 is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010063
Balint Dobszay719ba9c2021-03-26 16:23:18 +010064- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the
65 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided.
66
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010067- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
68 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
69 the RW sections in RAM, while leaving the RO sections in place. This option
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060070 enable this use-case. For now, this option is only supported
71 when RESET_TO_BL2 is set to '1'.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010072
73- ``BL31``: This is an optional build option which specifies the path to
74 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
75 be built.
76
77- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
78 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
79 this file name will be used to save the key.
80
81- ``BL32``: This is an optional build option which specifies the path to
82 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
83 be built.
84
85- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
86 Trusted OS Extra1 image for the ``fip`` target.
87
88- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
89 Trusted OS Extra2 image for the ``fip`` target.
90
91- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
92 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
93 this file name will be used to save the key.
94
95- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
96 ``fip`` target in case TF-A BL2 is used.
97
98- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
99 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
100 this file name will be used to save the key.
101
102- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
103 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
104 If enabled, it is needed to use a compiler that supports the option
105 ``-mbranch-protection``. Selects the branch protection features to use:
106- 0: Default value turns off all types of branch protection
107- 1: Enables all types of branch protection features
108- 2: Return address signing to its standard level
109- 3: Extend the signing to include leaf functions
Alexei Fedorove039e482020-06-19 14:33:49 +0100110- 4: Turn on branch target identification mechanism
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100111
112 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
113 and resulting PAuth/BTI features.
114
115 +-------+--------------+-------+-----+
116 | Value | GCC option | PAuth | BTI |
117 +=======+==============+=======+=====+
118 | 0 | none | N | N |
119 +-------+--------------+-------+-----+
120 | 1 | standard | Y | Y |
121 +-------+--------------+-------+-----+
122 | 2 | pac-ret | Y | N |
123 +-------+--------------+-------+-----+
124 | 3 | pac-ret+leaf | Y | N |
125 +-------+--------------+-------+-----+
Alexei Fedorove039e482020-06-19 14:33:49 +0100126 | 4 | bti | N | Y |
127 +-------+--------------+-------+-----+
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100128
Manish Pandey34a305e2021-10-21 21:53:49 +0100129 This option defaults to 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100130 Note that Pointer Authentication is enabled for Non-secure world
131 irrespective of the value of this option if the CPU supports it.
132
133- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
134 compilation of each build. It must be set to a C string (including quotes
135 where applicable). Defaults to a string that contains the time and date of
136 the compilation.
137
138- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
139 build to be uniquely identified. Defaults to the current git commit id.
140
Grant Likely388248a2020-07-30 08:50:10 +0100141- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build``
142
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100143- ``CFLAGS``: Extra user options appended on the compiler's command line in
144 addition to the options set by the build system.
145
146- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
147 release several CPUs out of reset. It can take either 0 (several CPUs may be
148 brought up) or 1 (only one CPU will ever be brought up during cold reset).
149 Default is 0. If the platform always brings up a single CPU, there is no
150 need to distinguish between primary and secondary CPUs and the boot path can
151 be optimised. The ``plat_is_my_cpu_primary()`` and
152 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
153 to be implemented in this case.
154
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100155- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
156 Defaults to ``tbbr``.
157
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100158- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
159 register state when an unexpected exception occurs during execution of
160 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
161 this is only enabled for a debug build of the firmware.
162
163- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
164 certificate generation tool to create new keys in case no valid keys are
165 present or specified. Allowed options are '0' or '1'. Default is '1'.
166
167- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
168 the AArch32 system registers to be included when saving and restoring the
169 CPU context. The option must be set to 0 for AArch64-only platforms (that
170 is on hardware that does not implement AArch32, or at least not at EL1 and
171 higher ELs). Default value is 1.
172
173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
174 registers to be included when saving and restoring the CPU context. Default
175 is 0.
176
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000177- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension
178 registers in cpu context. This must be enabled, if the platform wants to use
179 this feature in the Secure world and MTE is enabled at ELX. This flag can
180 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
181 Default value is 0.
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +0100182
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000183- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV
184 registers to be saved/restored when entering/exiting an EL2 execution
185 context. This flag can take values 0 to 2, to align with the
186 ``FEATURE_DETECTION`` mechanism. Default value is 0.
187
188- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer
189 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers
190 to be included when saving and restoring the CPU context as part of world
191 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION``
192 mechanism. Default value is 0.
193
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100194 Note that Pointer Authentication is enabled for Non-secure world irrespective
195 of the value of this flag if the CPU supports it.
196
197- ``DEBUG``: Chooses between a debug and release build. It can take either 0
198 (release) or 1 (debug) as values. 0 is the default.
199
Sumit Garg392e4df2019-11-15 10:43:00 +0530200- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the
201 authenticated decryption algorithm to be used to decrypt firmware/s during
202 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of
203 this flag is ``none`` to disable firmware decryption which is an optional
Manish Pandey34a305e2021-10-21 21:53:49 +0100204 feature as per TBBR.
Sumit Garg392e4df2019-11-15 10:43:00 +0530205
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100206- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
207 of the binary image. If set to 1, then only the ELF image is built.
208 0 is the default.
209
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000210- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented
211 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms
212 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU,
213 check the latest Arm ARM.
214
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100215- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
216 Board Boot authentication at runtime. This option is meant to be enabled only
217 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
218 flag has to be enabled. 0 is the default.
219
220- ``E``: Boolean option to make warnings into errors. Default is 1.
221
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +0000222 When specifying higher warnings levels (``W=1`` and higher), this option
223 defaults to 0. This is done to encourage contributors to use them, as they
224 are expected to produce warnings that would otherwise fail the build. New
225 contributions are still expected to build with ``W=0`` and ``E=1`` (the
226 default).
227
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100228- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
229 the normal boot flow. It must specify the entry point address of the EL3
230 payload. Please refer to the "Booting an EL3 payload" section for more
231 details.
232
Chris Kay925fda42021-05-25 10:42:56 +0100233- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters
234 (also known as group 1 counters). These are implementation-defined counters,
235 and as such require additional platform configuration. Default is 0.
236
Chris Kayf11909f2021-08-19 11:21:52 +0100237- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which
238 allows platforms with auxiliary counters to describe them via the
239 ``HW_CONFIG`` device tree blob. Default is 0.
240
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100241- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
242 are compiled out. For debug builds, this option defaults to 1, and calls to
243 ``assert()`` are left in place. For release builds, this option defaults to 0
244 and calls to ``assert()`` function are compiled out. This option can be set
245 independently of ``DEBUG``. It can also be used to hide any auxiliary code
246 that is only required for the assertion and does not fit in the assertion
247 itself.
248
Alexei Fedorovb8f26e92020-02-06 17:11:03 +0000249- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100250 dumps or not. It is supported in both AArch64 and AArch32. However, in
251 AArch32 the format of the frame records are not defined in the AAPCS and they
252 are defined by the implementation. This implementation of backtrace only
253 supports the format used by GCC when T32 interworking is disabled. For this
254 reason enabling this option in AArch32 will force the compiler to only
255 generate A32 code. This option is enabled by default only in AArch64 debug
256 builds, but this behaviour can be overridden in each platform's Makefile or
257 in the build command line.
258
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000259- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit
260 extensions. This flag can take the values 0 to 2, to align with the
261 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature
262 available on v8.4 onwards. Some v8.2 implementations also implement an AMU
263 and this option can be used to enable this feature on those systems as well.
264 This flag can take the values 0 to 2, the default is 0.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000265
266- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1``
267 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6
268 onwards. This flag can take the values 0 to 2, to align with the
269 ``FEATURE_DETECTION`` mechanism. Default value is ``0``.
270
271- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2``
272 extension. It allows access to the SCXTNUM_EL2 (Software Context Number)
273 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an
274 optional feature available on Arm v8.0 onwards. This flag can take values
275 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
276 Default value is ``0``.
277
278- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent
279 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3.
280 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4
281 and upwards. This flag can take the values 0 to 2, to align with the
282 ``FEATURE_DETECTION`` mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000283
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000284- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000285 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer
286 Physical Offset register) during EL2 to EL3 context save/restore operations.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000287 Its a mandatory architectural feature and is enabled from v8.6 and upwards.
288 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
289 mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000290
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000291- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps)
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000292 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000293 Read Trap Register) during EL2 to EL3 context save/restore operations.
294 Its a mandatory architectural feature and is enabled from v8.6 and upwards.
295 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
296 mechanism. Default value is ``0``.
297
298- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to
299 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as
300 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a
301 mandatory architectural feature and is enabled from v8.7 and upwards. This
302 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
303 mechanism. Default value is ``0``.
304
305- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged
306 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a
307 permission fault for any privileged data access from EL1/EL2 to virtual
308 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a
309 mandatory architectural feature and is enabled from v8.1 and upwards. This
310 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
311 mechanism. Default value is ``0``.
312
313- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension.
314 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This
315 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400316 mechanism. Default value is ``0``.
317
318- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP``
319 extension. This feature is only supported in AArch64 state. This flag can
320 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
321 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from
322 Armv8.5 onwards.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000323
Andre Przywara46880dc2022-11-17 16:42:09 +0000324- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB``
325 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and
326 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or
327 later CPUs. It is enabled from v8.5 and upwards and if needed can be
328 overidden from platforms explicitly.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000329
330- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2)
331 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4.
332 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
333 mechanism. Default is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000334
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100335- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed
336 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature
337 available on Arm v8.6. This flag can take values 0 to 2, to align with the
338 ``FEATURE_DETECTION`` mechanism. Default is ``0``.
339
340 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets
341 delayed by the amount of value in ``TWED_DELAY``.
342
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000343- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization
344 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register
345 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory
346 architectural feature and is enabled from v8.1 and upwards. It can take
347 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
348 Default value is ``0``.
johpow01f91e59f2021-08-04 19:38:18 -0500349
Mark Brownc37eee72023-03-14 20:13:03 +0000350- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to
351 allow access to TCR2_EL2 (extended translation control) from EL2 as
352 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a
353 mandatory architectural feature and is enabled from v8.9 and upwards. This
354 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
355 mechanism. Default value is ``0``.
356
Mark Brown293a6612023-03-14 20:48:43 +0000357- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE
358 at EL2 and below, and context switch relevant registers. This flag
359 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
360 mechanism. Default value is ``0``.
361
362- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE
363 at EL2 and below, and context switch relevant registers. This flag
364 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
365 mechanism. Default value is ``0``.
366
367- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE
368 at EL2 and below, and context switch relevant registers. This flag
369 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
370 mechanism. Default value is ``0``.
371
372- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE
373 at EL2 and below, and context switch relevant registers. This flag
374 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
375 mechanism. Default value is ``0``.
376
Mark Brown326f2952023-03-14 21:33:04 +0000377- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to
378 allow use of Guarded Control Stack from EL2 as well as adding the GCS
379 registers to the EL2 context save/restore operations. This flag can take
380 the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
381 Default value is ``0``.
382
Sandrine Bailleux11427302019-12-17 09:38:08 +0100383- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
zelalem-aweked5f45272019-11-12 16:20:17 -0600384 support in GCC for TF-A. This option is currently only supported for
385 AArch64. Default is 0.
386
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000387- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100388 feature. MPAM is an optional Armv8.4 extension that enables various memory
389 system components and resources to define partitions; software running at
390 various ELs can assign themselves to desired partition to control their
391 performance aspects.
392
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000393 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
394 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to
395 access their own MPAM registers without trapping into EL3. This option
396 doesn't make use of partitioning in EL3, however. Platform initialisation
397 code should configure and use partitions in EL3 as required. This option
398 defaults to ``0``.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100399
Chris Kay03be39d2021-05-05 13:38:30 +0100400- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power
401 Mitigation Mechanism supported by certain Arm cores, which allows the SoC
402 firmware to detect and limit high activity events to assist in SoC processor
403 power domain dynamic power budgeting and limit the triggering of whole-rail
404 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``.
405
406- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which
407 allows platforms with cores supporting MPMM to describe them via the
408 ``HW_CONFIG`` device tree blob. Default is 0.
409
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100410- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
411 support within generic code in TF-A. This option is currently only supported
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600412 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and
413 in BL32 (SP_min) for AARCH32. Default is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100414
415- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
416 Measurement Framework(PMF). Default is 0.
417
418- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
419 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
420 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
421 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
422 software.
423
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000424- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm
425 Management Extension. This flag can take the values 0 to 2, to align with
426 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently
427 an experimental feature.
Zelalem Aweke4d37db82021-07-11 18:33:20 -0500428
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100429- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
430 instrumentation which injects timestamp collection points into TF-A to
431 allow runtime performance to be measured. Currently, only PSCI is
432 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
433 as well. Default is 0.
434
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000435- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension
johpow019baade32021-07-08 14:14:00 -0500436 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share
437 registers so are enabled together. Using this option without
438 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure
439 world to trap to EL3. SME is an optional architectural feature for AArch64
440 and TF-A support is experimental. At this time, this build option cannot be
Manish Pandey247e5c32021-11-15 15:29:08 +0000441 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000442 build with these options will fail. This flag can take the values 0 to 2, to
443 align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
johpow019baade32021-07-08 14:14:00 -0500444
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000445- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension
446 version 2 (SME2) for the non-secure world only. SME2 is an optional
447 architectural feature for AArch64 and TF-A support is experimental.
448 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME
449 accesses will still be trapped. This flag can take the values 0 to 2, to
450 align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
451
johpow019baade32021-07-08 14:14:00 -0500452- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix
453 Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS
454 must also be set to use this. If enabling this, the secure world MUST
455 handle context switching for SME, SVE, and FPU/SIMD registers to ensure that
456 no data is leaked to non-secure world. This is experimental. Default is 0.
457
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +0000458- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100459 extensions. This is an optional architectural feature for AArch64.
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +0000460 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
461 mechanism. The default is 2 but is automatically disabled when the target
462 architecture is AArch32.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100463
Jayanth Dodderi Chidanandd62c6812023-03-07 10:43:19 +0000464- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100465 (SVE) for the Non-secure world only. SVE is an optional architectural feature
466 for AArch64. Note that when SVE is enabled for the Non-secure world, access
Max Shvetsovc4502772021-03-22 11:59:37 +0000467 to SIMD and floating-point functionality from the Secure world is disabled by
468 default and controlled with ENABLE_SVE_FOR_SWD.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100469 This is to avoid corruption of the Non-secure world data in the Z-registers
470 which are aliased by the SIMD and FP registers. The build option is not
471 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
Jayanth Dodderi Chidanandf3d308b2023-04-03 11:24:26 +0100472 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` enabled.
473 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
474 mechanism. The default is 2 but is automatically disabled when
475 ENABLE_SME_FOR_NS is enabled ( set to 1 or 2) since SME encompasses SVE.
476 At this time, this build option cannot be used on systems that have SPM_MM
477 enabled.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100478
Max Shvetsovc4502772021-03-22 11:59:37 +0000479- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
480 SVE is an optional architectural feature for AArch64. Note that this option
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000481 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it
482 is automatically disabled when the target architecture is AArch32.
Max Shvetsovc4502772021-03-22 11:59:37 +0000483
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100484- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
485 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
486 default value is set to "none". "strong" is the recommended stack protection
487 level if this feature is desired. "none" disables the stack protection. For
488 all values other than "none", the ``plat_get_stack_protector_canary()``
489 platform hook needs to be implemented. The value is passed as the last
490 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
491
Sumit Gargc0c369c2019-11-15 18:47:53 +0530492- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This
Manish Pandey34a305e2021-10-21 21:53:49 +0100493 flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530494
495- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload.
Manish Pandey34a305e2021-10-21 21:53:49 +0100496 This flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530497
498- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could
499 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends
Manish Pandey34a305e2021-10-21 21:53:49 +0100500 on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530501
502- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector
503 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT``
Manish Pandey34a305e2021-10-21 21:53:49 +0100504 build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530505
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100506- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
507 deprecated platform APIs, helper functions or drivers within Trusted
508 Firmware as error. It can take the value 1 (flag the use of deprecated
509 APIs as error) or 0. The default is 0.
510
511- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
512 targeted at EL3. When set ``0`` (default), no exceptions are expected or
Raghu Krishnamurthy669bf402022-07-25 14:44:33 -0700513 handled at EL3, and a panic will result. The exception to this rule is when
514 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions
515 occuring during normal world execution, are trapped to EL3. Any exception
516 trapped during secure world execution are trapped to the SPMC. This is
517 supported only for AArch64 builds.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100518
Javier Almansa Sobrino0d1f6b12020-09-18 16:47:07 +0100519- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when
520 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``.
521 Default value is 40 (LOG_LEVEL_INFO).
522
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100523- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
524 injection from lower ELs, and this build option enables lower ELs to use
525 Error Records accessed via System Registers to inject faults. This is
526 applicable only to AArch64 builds.
527
528 This feature is intended for testing purposes only, and is advisable to keep
529 disabled for production images.
530
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000531- ``FEATURE_DETECTION``: Boolean option to enable the architectural features
532 detection mechanism. It detects whether the Architectural features enabled
533 through feature specific build flags are supported by the PE or not by
534 validating them either at boot phase or at runtime based on the value
535 possessed by the feature flag (0 to 2) and report error messages at an early
536 stage.
537
538 This prevents and benefits us from EL3 runtime exceptions during context save
539 and restore routines guarded by these build flags. Henceforth validating them
540 before their usage provides more control on the actions taken under them.
541
542 The mechanism permits the build flags to take values 0, 1 or 2 and
543 evaluates them accordingly.
544
545 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example:
546
547 ::
548
549 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time.
550 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime.
551 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime.
552
553 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to
554 0, feature is disabled statically during compilation. If it is defined as 1,
555 feature is validated, wherein FEAT_HCX is detected at boot time. In case not
556 implemented by the PE, a hard panic is generated. Finally, if the flag is set
557 to 2, feature is validated at runtime.
558
559 Note that the entire implementation is divided into two phases, wherein as
560 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not
561 supported and is planned to be handled explicilty in phase-2 implementation.
562
563 FEATURE_DETECTION macro is disabled by default, and is currently an
564 experimental procedure. Platforms can explicitly make use of this by
565 mechanism, by enabling it to validate whether they have set their build flags
566 properly at an early phase.
567
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100568- ``FIP_NAME``: This is an optional build option which specifies the FIP
569 filename for the ``fip`` target. Default is ``fip.bin``.
570
571- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
572 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
573
Sumit Gargc0c369c2019-11-15 18:47:53 +0530574- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values:
575
576 ::
577
578 0: Encryption is done with Secret Symmetric Key (SSK) which is common
579 for a class of devices.
580 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is
581 unique per device.
582
Manish Pandey34a305e2021-10-21 21:53:49 +0100583 This flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530584
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100585- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
586 tool to create certificates as per the Chain of Trust described in
587 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
588 include the certificates in the FIP and FWU_FIP. Default value is '0'.
589
590 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
591 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
592 the corresponding certificates, and to include those certificates in the
593 FIP and FWU_FIP.
594
595 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
596 images will not include support for Trusted Board Boot. The FIP will still
597 include the corresponding certificates. This FIP can be used to verify the
598 Chain of Trust on the host machine through other mechanisms.
599
600 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
601 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
602 will not include the corresponding certificates, causing a boot failure.
603
604- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
605 inherent support for specific EL3 type interrupts. Setting this build option
606 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -0500607 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and
608 :ref:`Interrupt Management Framework<Interrupt Management Framework>`.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100609 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
610 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
611 the Secure Payload interrupts needs to be synchronously handed over to Secure
612 EL1 for handling. The default value of this option is ``0``, which means the
613 Group 0 interrupts are assumed to be handled by Secure EL1.
614
Manish Pandey0e3379d2022-10-10 11:43:08 +0100615- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError
616 Interrupts, resulting from errors in NS world, will be always trapped in
617 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions
618 will be trapped in the current exception level (or in EL1 if the current
619 exception level is EL0).
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100620
621- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
622 software operations are required for CPUs to enter and exit coherency.
623 However, newer systems exist where CPUs' entry to and exit from coherency
624 is managed in hardware. Such systems require software to only initiate these
625 operations, and the rest is managed in hardware, minimizing active software
626 management. In such systems, this boolean option enables TF-A to carry out
627 build and run-time optimizations during boot and power management operations.
628 This option defaults to 0 and if it is enabled, then it implies
629 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
630
631 If this flag is disabled while the platform which TF-A is compiled for
632 includes cores that manage coherency in hardware, then a compilation error is
633 generated. This is based on the fact that a system cannot have, at the same
634 time, cores that manage coherency in hardware and cores that don't. In other
635 words, a platform cannot have, at the same time, cores that require
636 ``HW_ASSISTED_COHERENCY=1`` and cores that require
637 ``HW_ASSISTED_COHERENCY=0``.
638
639 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
640 translation library (xlat tables v2) must be used; version 1 of translation
641 library is not supported.
642
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000643- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000644 bottom, higher addresses at the top. This build flag can be set to '1' to
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000645 invert this behavior. Lower addresses will be printed at the top and higher
646 addresses at the bottom.
647
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100648- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
649 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
650 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
651 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
652 images.
653
654- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
655 used for generating the PKCS keys and subsequent signing of the certificate.
Lionel Debievefefeffb2022-11-14 11:03:42 +0100656 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular``
657 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1
658 RSA 1.5 algorithm which is not TBBR compliant and is retained only for
659 compatibility. The default value of this flag is ``rsa`` which is the TBBR
660 compliant PKCS#1 RSA 2.1 scheme.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100661
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300662- ``KEY_SIZE``: This build flag enables the user to select the key size for
663 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
664 depend on the chosen algorithm and the cryptographic module.
665
Lionel Debievefefeffb2022-11-14 11:03:42 +0100666 +---------------------------+------------------------------------+
667 | KEY_ALG | Possible key sizes |
668 +===========================+====================================+
669 | rsa | 1024 , 2048 (default), 3072, 4096* |
670 +---------------------------+------------------------------------+
671 | ecdsa | unavailable |
672 +---------------------------+------------------------------------+
673 | ecdsa-brainpool-regular | unavailable |
674 +---------------------------+------------------------------------+
675 | ecdsa-brainpool-twisted | unavailable |
676 +---------------------------+------------------------------------+
677
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300678
679 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1.
680 Only 3072 bits size is available with CryptoCell 712 SBROM release 2.
681
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100682- ``HASH_ALG``: This build flag enables the user to select the secure hash
683 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
684 The default value of this flag is ``sha256``.
685
686- ``LDFLAGS``: Extra user options appended to the linkers' command line in
687 addition to the one set by the build system.
688
689- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
690 output compiled into the build. This should be one of the following:
691
692 ::
693
694 0 (LOG_LEVEL_NONE)
695 10 (LOG_LEVEL_ERROR)
696 20 (LOG_LEVEL_NOTICE)
697 30 (LOG_LEVEL_WARNING)
698 40 (LOG_LEVEL_INFO)
699 50 (LOG_LEVEL_VERBOSE)
700
701 All log output up to and including the selected log level is compiled into
702 the build. The default value is 40 in debug builds and 20 in release builds.
703
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000704- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
Manish V Badarkhe92de80a2021-12-16 10:41:47 +0000705 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to
706 provide trust that the code taking the measurements and recording them has
707 not been tampered with.
Sandrine Bailleux533d8b32021-06-10 11:18:04 +0200708
Manish Pandey34a305e2021-10-21 21:53:49 +0100709 This option defaults to 0.
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000710
Manish V Badarkhe8564f772022-02-14 18:31:16 +0000711- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust
712 for Measurement (DRTM). This feature has trust dependency on BL31 for taking
713 the measurements and recording them as per `PSA DRTM specification`_. For
714 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can
715 be used and for the platforms which use ``RESET_TO_BL31`` platform owners
Manish V Badarkhebbe1e422023-02-20 22:44:03 +0000716 should have mechanism to authenticate BL31. This is an experimental feature.
Manish V Badarkhe8564f772022-02-14 18:31:16 +0000717
718 This option defaults to 0.
719
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100720- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
721 specifies the file that contains the Non-Trusted World private key in PEM
722 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
723
724- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
725 optional. It is only needed if the platform makefile specifies that it
726 is required in order to build the ``fwu_fip`` target.
727
728- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
729 contents upon world switch. It can take either 0 (don't save and restore) or
730 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
731 wants the timer registers to be saved and restored.
732
733- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
734 for the BL image. It can be either 0 (include) or 1 (remove). The default
735 value is 0.
736
737- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
738 the underlying hardware is not a full PL011 UART but a minimally compliant
739 generic UART, which is a subset of the PL011. The driver will not access
740 any register that is not part of the SBSA generic UART specification.
741 Default value is 0 (a full PL011 compliant UART is present).
742
743- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
744 must be subdirectory of any depth under ``plat/``, and must contain a
745 platform makefile named ``platform.mk``. For example, to build TF-A for the
746 Arm Juno board, select PLAT=juno.
747
748- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
749 instead of the normal boot flow. When defined, it must specify the entry
750 point address for the preloaded BL33 image. This option is incompatible with
751 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
752 over ``PRELOADED_BL33_BASE``.
753
754- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
755 vector address can be programmed or is fixed on the platform. It can take
756 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
757 programmable reset address, it is expected that a CPU will start executing
758 code directly at the right address, both on a cold and warm reset. In this
759 case, there is no need to identify the entrypoint on boot and the boot path
760 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
761 does not need to be implemented in this case.
762
763- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
764 possible for the PSCI power-state parameter: original and extended State-ID
765 formats. This flag if set to 1, configures the generic PSCI layer to use the
766 extended format. The default value of this flag is 0, which means by default
767 the original power-state format is used by the PSCI implementation. This flag
768 should be specified by the platform makefile and it governs the return value
769 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
770 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
771 set to 1 as well.
772
Wing Li1e9b68a2023-01-26 18:33:36 -0800773- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI
774 OS-initiated mode. This option defaults to 0.
775
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000776- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100777 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000778 or later CPUs. This flag can take the values 0 to 2, to align with the
779 ``FEATURE_DETECTION`` mechanism.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100780
Manish Pandey0e3379d2022-10-10 11:43:08 +0100781 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST_NS`` must also be
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100782 set to ``1``.
783
784 This option is disabled by default.
785
786- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
787 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
788 entrypoint) or 1 (CPU reset to BL31 entrypoint).
789 The default value is 0.
790
791- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
792 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
793 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
794 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
795
796- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
Max Shvetsov06dba292019-12-06 11:50:12 +0000797 file that contains the ROT private key in PEM format and enforces public key
798 hash generation. If ``SAVE_KEYS=1``, this
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100799 file name will be used to save the key.
800
801- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
802 certificate generation tool to save the keys used to establish the Chain of
803 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
804
805- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
806 If a SCP_BL2 image is present then this option must be passed for the ``fip``
807 target.
808
809- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
810 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
811 this file name will be used to save the key.
812
813- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
814 optional. It is only needed if the platform makefile specifies that it
815 is required in order to build the ``fwu_fip`` target.
816
817- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
818 Delegated Exception Interface to BL31 image. This defaults to ``0``.
819
820 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
821 set to ``1``.
822
823- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
824 isolated on separate memory pages. This is a trade-off between security and
825 memory usage. See "Isolating code and read-only data on separate memory
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100826 pages" section in :ref:`Firmware Design`. This flag is disabled by default
827 and affects all BL images.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100828
Samuel Holland31a14e12018-10-17 21:40:18 -0500829- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
830 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
831 allocated in RAM discontiguous from the loaded firmware image. When set, the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000832 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and
Samuel Holland31a14e12018-10-17 21:40:18 -0500833 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
834 sections are placed in RAM immediately following the loaded firmware image.
835
Jiafei Pan0824b452022-02-24 10:47:33 +0800836- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the
837 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM
838 discontiguous from loaded firmware images. When set, the platform need to
839 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This
840 flag is disabled by default and NOLOAD sections are placed in RAM immediately
841 following the loaded firmware image.
842
Jeremy Linton684a0792021-01-26 22:42:03 -0600843- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration
844 access requests via a standard SMCCC defined in `DEN0115`_. When combined with
845 UEFI+ACPI this can provide a certain amount of OS forward compatibility
846 with newer platforms that aren't ECAM compliant.
847
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100848- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
849 This build option is only valid if ``ARCH=aarch64``. The value should be
850 the path to the directory containing the SPD source, relative to
851 ``services/spd/``; the directory is expected to contain a makefile called
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100852 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in
853 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher
854 cannot be enabled when the ``SPM_MM`` option is enabled.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100855
856- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
857 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
858 execution in BL1 just before handing over to BL31. At this point, all
859 firmware images have been loaded in memory, and the MMU and caches are
860 turned off. Refer to the "Debugging options" section for more details.
861
Marc Bonniciabaac162021-12-01 18:00:40 +0000862- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM
863 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
864 component runs at the EL3 exception level. The default value is ``0`` (
865 disabled). This configuration supports pre-Armv8.4 platforms (aka not
866 implementing the ``FEAT_SEL2`` extension). This is an experimental feature.
867
Jens Wiklanderba0ed3e2022-12-14 17:02:16 +0100868- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM
869 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to
870 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading
871 mechanism should be used.
872
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000873- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100874 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
Marc Bonniciabaac162021-12-01 18:00:40 +0000875 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2``
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100876 extension. This is the default when enabling the SPM Dispatcher. When
877 disabled (0) it indicates the SPMC component runs at the S-EL1 execution
Marc Bonniciabaac162021-12-01 18:00:40 +0000878 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations
879 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2``
880 extension).
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100881
Paul Beesleyfe975b42019-09-16 11:29:03 +0000882- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100883 Partition Manager (SPM) implementation. The default value is ``0``
884 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is
885 enabled (``SPD=spmd``).
Paul Beesleyfe975b42019-09-16 11:29:03 +0000886
Manish Pandey3f90ad72020-01-14 11:52:05 +0000887- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100888 description of secure partitions. The build system will parse this file and
889 package all secure partition blobs into the FIP. This file is not
890 necessarily part of TF-A tree. Only available when ``SPD=spmd``.
Manish Pandey3f90ad72020-01-14 11:52:05 +0000891
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100892- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
893 secure interrupts (caught through the FIQ line). Platforms can enable
894 this directive if they need to handle such interruption. When enabled,
895 the FIQ are handled in monitor mode and non secure world is not allowed
896 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
897 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
898
Mark Brown64869972022-04-20 18:14:32 +0100899- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3.
900 Platforms can configure this if they need to lower the hardware
901 limit, for example due to asymmetric configuration or limitations of
902 software run at lower ELs. The default is the architectural maximum
903 of 2048 which should be suitable for most configurations, the
904 hardware will limit the effective VL to the maximum physically supported
905 VL.
906
Jayanth Dodderi Chidanand7c7faff2022-10-11 17:16:07 +0100907- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True
908 Random Number Generator Interface to BL31 image. This defaults to ``0``.
909
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100910- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
911 Boot feature. When set to '1', BL1 and BL2 images include support to load
912 and verify the certificates and images in a FIP, and BL1 includes support
913 for the Firmware Update. The default value is '0'. Generation and inclusion
914 of certificates in the FIP and FWU_FIP depends upon the value of the
915 ``GENERATE_COT`` option.
916
917 .. warning::
918 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
919 already exist in disk, they will be overwritten without further notice.
920
921- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
922 specifies the file that contains the Trusted World private key in PEM
923 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
924
925- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
926 synchronous, (see "Initializing a BL32 Image" section in
927 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
928 synchronous method) or 1 (BL32 is initialized using asynchronous method).
929 Default is 0.
930
931- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
932 routing model which routes non-secure interrupts asynchronously from TSP
933 to EL3 causing immediate preemption of TSP. The EL3 is responsible
934 for saving and restoring the TSP context in this routing model. The
935 default routing model (when the value is 0) is to route non-secure
936 interrupts to TSP allowing it to save its context and hand over
937 synchronously to EL3 via an SMC.
938
939 .. note::
940 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
941 must also be set to ``1``.
942
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100943- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of
944 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set
945 this delay. It can take values in the range (0-15). Default value is ``0``
946 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed.
947 Platforms need to explicitly update this value based on their requirements.
948
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100949- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
950 linker. When the ``LINKER`` build variable points to the armlink linker,
951 this flag is enabled automatically. To enable support for armlink, platforms
952 will have to provide a scatter file for the BL image. Currently, Tegra
953 platforms use the armlink support to compile BL3-1 images.
954
955- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
956 memory region in the BL memory map or not (see "Use of Coherent memory in
957 TF-A" section in :ref:`Firmware Design`). It can take the value 1
958 (Coherent memory region is included) or 0 (Coherent memory region is
959 excluded). Default is 1.
960
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100961- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature
962 exposing a virtual filesystem interface through BL31 as a SiP SMC function.
963 Default is 0.
964
Louis Mayencourt6b232d92020-02-28 16:57:30 +0000965- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
966 firmware configuration framework. This will move the io_policies into a
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100967 configuration device tree, instead of static structure in the code base.
968
Manish V Badarkhead339892020-06-29 10:32:53 +0100969- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors
970 at runtime using fconf. If this flag is enabled, COT descriptors are
971 statically captured in tb_fw_config file in the form of device tree nodes
972 and properties. Currently, COT descriptors used by BL2 are moved to the
973 device tree and COT descriptors used by BL1 are retained in the code
Manish Pandey34a305e2021-10-21 21:53:49 +0100974 base statically.
Manish V Badarkhead339892020-06-29 10:32:53 +0100975
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100976- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in
977 runtime using firmware configuration framework. The platform specific SDEI
978 shared and private events configuration is retrieved from device tree rather
Manish Pandey34a305e2021-10-21 21:53:49 +0100979 than static C structures at compile time. This is only supported if
980 SDEI_SUPPORT build flag is enabled.
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100981
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500982- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0
983 and Group1 secure interrupts using the firmware configuration framework. The
984 platform specific secure interrupt property descriptor is retrieved from
985 device tree in runtime rather than depending on static C structure at compile
Manish Pandey34a305e2021-10-21 21:53:49 +0100986 time.
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500987
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100988- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
989 This feature creates a library of functions to be placed in ROM and thus
990 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default
991 is 0.
992
993- ``V``: Verbose build. If assigned anything other than 0, the build commands
994 are printed. Default is 0.
995
996- ``VERSION_STRING``: String used in the log output for each TF-A image.
997 Defaults to a string formed by concatenating the version number, build type
998 and build string.
999
1000- ``W``: Warning level. Some compiler warning options of interest have been
1001 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
1002 each level enabling more warning options. Default is 0.
1003
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +00001004 This option is closely related to the ``E`` option, which enables
1005 ``-Werror``.
1006
1007 - ``W=0`` (default)
1008
1009 Enables a wide assortment of warnings, most notably ``-Wall`` and
1010 ``-Wextra``, as well as various bad practices and things that are likely to
1011 result in errors. Includes some compiler specific flags. No warnings are
1012 expected at this level for any build.
1013
1014 - ``W=1``
1015
1016 Enables warnings we want the generic build to include but are too time
1017 consuming to fix at the moment. It re-enables warnings taken out for
1018 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected
1019 to eventually be merged into ``W=0``. Some warnings are expected on some
1020 builds, but new contributions should not introduce new ones.
1021
1022 - ``W=2`` (recommended)
1023
1024 Enables warnings we want the generic build to include but cannot be enabled
1025 due to external libraries. This level is expected to eventually be merged
1026 into ``W=0``. Lots of warnings are expected, primarily from external
1027 libraries like zlib and compiler-rt, but new controbutions should not
1028 introduce new ones.
1029
1030 - ``W=3``
1031
1032 Enables warnings that are informative but not necessary and generally too
1033 verbose and frequently ignored. A very large number of warnings are
1034 expected.
1035
1036 The exact set of warning flags depends on the compiler and TF-A warning
1037 level, however they are all succinctly set in the top-level Makefile. Please
1038 refer to the `GCC`_ or `Clang`_ documentation for more information on the
1039 individual flags.
1040
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001041- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
1042 the CPU after warm boot. This is applicable for platforms which do not
1043 require interconnect programming to enable cache coherency (eg: single
1044 cluster platforms). If this option is enabled, then warm boot path
1045 enables D-caches immediately after enabling MMU. This option defaults to 0.
1046
Manish V Badarkhe75c972a2020-03-22 05:06:38 +00001047- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
1048 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
1049 default value of this flag is ``no``. Note this option must be enabled only
1050 for ARM architecture greater than Armv8.5-A.
1051
Manish V Badarkhea59fa012020-07-31 08:38:49 +01001052- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
1053 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
1054 The default value of this flag is ``0``.
1055
1056 ``AT`` speculative errata workaround disables stage1 page table walk for
1057 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point
1058 produces either the correct result or failure without TLB allocation.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +01001059
1060 This boolean option enables errata for all below CPUs.
1061
Manish V Badarkhea59fa012020-07-31 08:38:49 +01001062 +---------+--------------+-------------------------+
1063 | Errata | CPU | Workaround Define |
1064 +=========+==============+=========================+
1065 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` |
1066 +---------+--------------+-------------------------+
1067 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` |
1068 +---------+--------------+-------------------------+
1069 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` |
1070 +---------+--------------+-------------------------+
1071 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` |
1072 +---------+--------------+-------------------------+
1073 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` |
1074 +---------+--------------+-------------------------+
1075
1076 .. note::
1077 This option is enabled by build only if platform sets any of above defines
1078 mentioned in ’Workaround Define' column in the table.
1079 If this option is enabled for the EL3 software then EL2 software also must
1080 implement this workaround due to the behaviour of the errata mentioned
1081 in new SDEN document which will get published soon.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +01001082
Manish Pandey7c6fcb42022-09-27 14:30:34 +01001083- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR
Varun Wadekar92234852020-06-12 10:11:28 -07001084 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
1085 This flag is disabled by default.
1086
Juan Pablo Conde52865522022-06-28 16:56:32 -04001087- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the
1088 host machine where a custom installation of OpenSSL is located, which is used
1089 to build the certificate generation, firmware encryption and FIP tools. If
1090 this option is not set, the default OS installation will be used.
Manish V Badarkhe3589b702020-07-29 10:58:44 +01001091
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -05001092- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for
1093 functions that wait for an arbitrary time length (udelay and mdelay). The
1094 default value is 0.
1095
Jayanth Dodderi Chidanand69316752022-05-09 12:33:03 +01001096- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record
1097 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an
1098 optional architectural feature for AArch64. This flag can take the values
1099 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0
1100 and it is automatically disabled when the target architecture is AArch32.
johpow0181865962022-01-28 17:06:20 -06001101
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001102- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer
Manish V Badarkhe20df29c2021-07-02 09:10:56 +01001103 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented
1104 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001105 feature for AArch64. This flag can take the values 0 to 2, to align with the
1106 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically
1107 disabled when the target architecture is AArch32.
Manish V Badarkhe20df29c2021-07-02 09:10:56 +01001108
Andre Przywara44e33e02022-11-17 16:42:09 +00001109- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system
Manish V Badarkhef356f7e2021-06-29 11:44:20 +01001110 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented
1111 but unused). This feature is available if trace unit such as ETMv4.x, and
Andre Przywara44e33e02022-11-17 16:42:09 +00001112 ETE(extending ETM feature) is implemented. This flag can take the values
1113 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0.
Manish V Badarkhef356f7e2021-06-29 11:44:20 +01001114
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +00001115- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers
Manish V Badarkhe51a97112021-07-08 09:33:18 +01001116 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused),
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +00001117 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align
1118 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default.
Manish V Badarkhe51a97112021-07-08 09:33:18 +01001119
Tamas Banc9ccc272022-01-18 16:20:47 +01001120- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA
1121 APIs on platforms that doesn't support RSS (providing Arm CCA HES
1122 functionalities). When enabled (``1``), a mocked version of the APIs are used.
1123 The default value is 0.
1124
Okash Khawaja037b56e2022-11-04 12:38:01 +00001125- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine
1126 ``plat_can_cmo`` which will return zero if cache management operations should
1127 be skipped and non-zero otherwise. By default, this option is disabled which
1128 means platform hook won't be checked and CMOs will always be performed when
1129 related functions are called.
1130
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001131GICv3 driver options
1132--------------------
1133
1134GICv3 driver files are included using directive:
1135
1136``include drivers/arm/gic/v3/gicv3.mk``
1137
1138The driver can be configured with the following options set in the platform
1139makefile:
1140
Andre Przywarae1cc1302020-03-25 15:50:38 +00001141- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3.
1142 Enabling this option will add runtime detection support for the
1143 GIC-600, so is safe to select even for a GIC500 implementation.
1144 This option defaults to 0.
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001145
Varun Wadekareea6dc12021-05-04 16:14:09 -07001146- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit
1147 for GIC-600 AE. Enabling this option will introduce support to initialize
1148 the FMU. Platforms should call the init function during boot to enable the
1149 FMU and its safety mechanisms. This option defaults to 0.
1150
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001151- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip
1152 functionality. This option defaults to 0
1153
1154- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation
1155 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore``
1156 functions. This is required for FVP platform which need to simulate GIC save
1157 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.
1158
Alexei Fedorov19705932020-04-06 19:00:35 +01001159- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver.
1160 This option defaults to 0.
1161
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001162- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended
1163 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.
1164
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001165Debugging options
1166-----------------
1167
1168To compile a debug version and make the build more verbose use
1169
1170.. code:: shell
1171
1172 make PLAT=<platform> DEBUG=1 V=1 all
1173
Daniel Boulbydf83a832022-05-03 16:46:16 +01001174AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools
1175(for example Arm-DS) might not support this and may need an older version of
1176DWARF symbols to be emitted by GCC. This can be achieved by using the
1177``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting
1178the version to 4 is recommended for Arm-DS.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001179
1180When debugging logic problems it might also be useful to disable all compiler
1181optimizations by using ``-O0``.
1182
1183.. warning::
1184 Using ``-O0`` could cause output images to be larger and base addresses
1185 might need to be recalculated (see the **Memory layout on Arm development
1186 platforms** section in the :ref:`Firmware Design`).
1187
1188Extra debug options can be passed to the build system by setting ``CFLAGS`` or
1189``LDFLAGS``:
1190
1191.. code:: shell
1192
1193 CFLAGS='-O0 -gdwarf-2' \
1194 make PLAT=<platform> DEBUG=1 V=1 all
1195
1196Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
1197ignored as the linker is called directly.
1198
1199It is also possible to introduce an infinite loop to help in debugging the
1200post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
1201``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common`
1202section. In this case, the developer may take control of the target using a
Daniel Boulbydf83a832022-05-03 16:46:16 +01001203debugger when indicated by the console output. When using Arm-DS, the following
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001204commands can be used:
1205
1206::
1207
1208 # Stop target execution
1209 interrupt
1210
1211 #
1212 # Prepare your debugging environment, e.g. set breakpoints
1213 #
1214
1215 # Jump over the debug loop
1216 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1217
1218 # Resume execution
1219 continue
1220
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001221Firmware update options
1222-----------------------
1223
1224- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used
1225 in defining the firmware update metadata structure. This flag is by default
1226 set to '2'.
1227
1228- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each
1229 firmware bank. Each firmware bank must have the same number of images as per
1230 the `PSA FW update specification`_.
1231 This flag is used in defining the firmware update metadata structure. This
1232 flag is by default set to '1'.
1233
Manish V Badarkheda87af12021-06-20 21:14:46 +01001234- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the
1235 `PSA FW update specification`_. The default value is 0, and this is an
1236 experimental feature.
1237 PSA firmware update implementation has some limitations, such as BL2 is
1238 not part of the protocol-updatable images, if BL2 needs to be updated, then
1239 it should be done through another platform-defined mechanism, and it assumes
1240 that the platform's hardware supports CRC32 instructions.
1241
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001242--------------
1243
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06001244*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
Jeremy Linton684a0792021-01-26 22:42:03 -06001245
1246.. _DEN0115: https://developer.arm.com/docs/den0115/latest
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001247.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
Manish V Badarkhe8564f772022-02-14 18:31:16 +00001248.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +00001249.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html
1250.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html