| Vijayenthiran Subramaniam | ad3fc76 | 2019-09-16 17:05:08 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef GIC600_MULTICHIP_PRIVATE_H |
| 8 | #define GIC600_MULTICHIP_PRIVATE_H |
| 9 | |
| 10 | #include <drivers/arm/gic600_multichip.h> |
| 11 | |
| 12 | #include "gicv3_private.h" |
| 13 | |
| 14 | /* GIC600 GICD multichip related offsets */ |
| 15 | #define GICD_CHIPSR U(0xC000) |
| 16 | #define GICD_DCHIPR U(0xC004) |
| 17 | #define GICD_CHIPR U(0xC008) |
| 18 | |
| 19 | /* GIC600 GICD multichip related masks */ |
| 20 | #define GICD_CHIPRx_PUP_BIT BIT_64(1) |
| 21 | #define GICD_CHIPRx_SOCKET_STATE BIT_64(0) |
| 22 | #define GICD_DCHIPR_PUP_BIT BIT_32(0) |
| 23 | #define GICD_CHIPSR_RTS_MASK (BIT_32(4) | BIT_32(5)) |
| 24 | |
| 25 | /* GIC600 GICD multichip related shifts */ |
| 26 | #define GICD_CHIPRx_ADDR_SHIFT 16 |
| 27 | #define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10 |
| 28 | #define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5 |
| 29 | #define GICD_CHIPSR_RTS_SHIFT 4 |
| 30 | #define GICD_DCHIPR_RT_OWNER_SHIFT 4 |
| 31 | |
| 32 | #define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0) |
| 33 | #define GICD_CHIPSR_RTS_STATE_UPDATING U(1) |
| 34 | #define GICD_CHIPSR_RTS_STATE_CONSISTENT U(2) |
| 35 | |
| 36 | /* SPI interrupt id minimum and maximum range */ |
| 37 | #define GIC600_SPI_ID_MIN 32 |
| 38 | #define GIC600_SPI_ID_MAX 960 |
| 39 | |
| 40 | /* Number of retries for PUP update */ |
| 41 | #define GICD_PUP_UPDATE_RETRIES 10000 |
| 42 | |
| 43 | #define SPI_MIN_INDEX 0 |
| 44 | #define SPI_MAX_INDEX 1 |
| 45 | |
| 46 | #define SPI_BLOCK_MIN_VALUE(spi_id_min) \ |
| 47 | (((spi_id_min) - GIC600_SPI_ID_MIN) / \ |
| 48 | GIC600_SPI_ID_MIN) |
| 49 | #define SPI_BLOCKS_VALUE(spi_id_min, spi_id_max) \ |
| 50 | (((spi_id_max) - (spi_id_min) + 1) / \ |
| 51 | GIC600_SPI_ID_MIN) |
| 52 | #define GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks) \ |
| 53 | (((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \ |
| 54 | ((spi_block_min) << GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT) | \ |
| 55 | ((spi_blocks) << GICD_CHIPRx_SPI_BLOCKS_SHIFT)) |
| 56 | |
| 57 | /* |
| 58 | * Multichip data assertion macros |
| 59 | */ |
| 60 | /* Set bits from 0 to ((spi_id_max + 1) / 32) */ |
| 61 | #define SPI_BLOCKS_TILL_MAX(spi_id_max) ((1 << (((spi_id_max) + 1) >> 5)) - 1) |
| 62 | /* Set bits from 0 to (spi_id_min / 32) */ |
| 63 | #define SPI_BLOCKS_TILL_MIN(spi_id_min) ((1 << ((spi_id_min) >> 5)) - 1) |
| 64 | /* Set bits from (spi_id_min / 32) to ((spi_id_max + 1) / 32) */ |
| 65 | #define BLOCKS_OF_32(spi_id_min, spi_id_max) \ |
| 66 | SPI_BLOCKS_TILL_MAX(spi_id_max) ^ \ |
| 67 | SPI_BLOCKS_TILL_MIN(spi_id_min) |
| 68 | |
| 69 | /******************************************************************************* |
| 70 | * GIC-600 multichip operation related helper functions |
| 71 | ******************************************************************************/ |
| 72 | static inline uint32_t read_gicd_dchipr(uintptr_t base) |
| 73 | { |
| 74 | return mmio_read_32(base + GICD_DCHIPR); |
| 75 | } |
| 76 | |
| 77 | static inline uint64_t read_gicd_chipr_n(uintptr_t base, uint8_t n) |
| 78 | { |
| 79 | return mmio_read_64(base + (GICD_CHIPR + (8U * n))); |
| 80 | } |
| 81 | |
| 82 | static inline uint32_t read_gicd_chipsr(uintptr_t base) |
| 83 | { |
| 84 | return mmio_read_32(base + GICD_CHIPSR); |
| 85 | } |
| 86 | |
| 87 | static inline void write_gicd_dchipr(uintptr_t base, uint32_t val) |
| 88 | { |
| 89 | mmio_write_32(base + GICD_DCHIPR, val); |
| 90 | } |
| 91 | |
| 92 | static inline void write_gicd_chipr_n(uintptr_t base, uint8_t n, uint64_t val) |
| 93 | { |
| 94 | mmio_write_64(base + (GICD_CHIPR + (8U * n)), val); |
| 95 | } |
| 96 | |
| 97 | #endif /* GIC600_MULTICHIP_PRIVATE_H */ |