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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Arm Fixed Virtual Platforms (FVP)
2=================================
3
4Fixed Virtual Platform (FVP) Support
5------------------------------------
6
7This section lists the supported Arm |FVP| platforms. Please refer to the FVP
8documentation for a detailed description of the model parameter options.
9
10The latest version of the AArch64 build of TF-A has been tested on the following
11Arm FVPs without shifted affinities, and that do not support threaded CPU cores
12(64-bit host machine only).
13
14.. note::
15 The FVP models used are Version 11.6 Build 45, unless otherwise stated.
16
17- ``FVP_Base_AEMv8A-AEMv8A``
18- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
19- ``FVP_Base_RevC-2xAEMv8A``
20- ``FVP_Base_Cortex-A32x4``
21- ``FVP_Base_Cortex-A35x4``
22- ``FVP_Base_Cortex-A53x4``
23- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
24- ``FVP_Base_Cortex-A55x4``
25- ``FVP_Base_Cortex-A57x1-A53x1``
26- ``FVP_Base_Cortex-A57x2-A53x4``
27- ``FVP_Base_Cortex-A57x4-A53x4``
28- ``FVP_Base_Cortex-A57x4``
Imre Kisf05a1622020-02-27 15:05:03 +010029- ``FVP_Base_Cortex-A65x4`` (Version 11.9 build 41)
30- ``FVP_Base_Cortex-A65AEx8`` (Version 11.9 build 41)
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010031- ``FVP_Base_Cortex-A72x4-A53x4``
32- ``FVP_Base_Cortex-A72x4``
33- ``FVP_Base_Cortex-A73x4-A53x4``
34- ``FVP_Base_Cortex-A73x4``
35- ``FVP_Base_Cortex-A75x4``
36- ``FVP_Base_Cortex-A76x4``
37- ``FVP_Base_Cortex-A76AEx4``
38- ``FVP_Base_Cortex-A76AEx8``
39- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
40- ``FVP_Base_Neoverse-N1x4``
41- ``FVP_Base_Zeusx4``
42- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
43- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
44- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
45- ``FVP_RD_N1Edge``
46- ``Foundation_Platform``
47
48The latest version of the AArch32 build of TF-A has been tested on the
49following Arm FVPs without shifted affinities, and that do not support threaded
50CPU cores (64-bit host machine only).
51
52- ``FVP_Base_AEMv8A-AEMv8A``
53- ``FVP_Base_Cortex-A32x4``
54
55.. note::
56 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
57 is not compatible with legacy GIC configurations. Therefore this FVP does not
58 support these legacy GIC configurations.
59
60The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
61FVP website`_. The Cortex-A models listed above are also available to download
62from `Arm's website`_.
63
64.. note::
65 The build numbers quoted above are those reported by launching the FVP
66 with the ``--version`` parameter.
67
68.. note::
69 Linaro provides a ramdisk image in prebuilt FVP configurations and full
70 file systems that can be downloaded separately. To run an FVP with a virtio
71 file system image an additional FVP configuration option
72 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
73 used.
74
75.. note::
76 The software will not work on Version 1.0 of the Foundation FVP.
77 The commands below would report an ``unhandled argument`` error in this case.
78
79.. note::
80 FVPs can be launched with ``--cadi-server`` option such that a
81 CADI-compliant debugger (for example, Arm DS-5) can connect to and control
82 its execution.
83
84.. warning::
85 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
86 the internal synchronisation timings changed compared to older versions of
87 the models. The models can be launched with ``-Q 100`` option if they are
88 required to match the run time characteristics of the older versions.
89
90All the above platforms have been tested with `Linaro Release 19.06`_.
91
92.. _build_options_arm_fvp_platform:
93
94Arm FVP Platform Specific Build Options
95---------------------------------------
96
97- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
98 build the topology tree within TF-A. By default TF-A is configured for dual
99 cluster topology and this option can be used to override the default value.
100
101- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
102 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
103 explained in the options below:
104
105 - ``FVP_CCI`` : The CCI driver is selected. This is the default
106 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
107 - ``FVP_CCN`` : The CCN driver is selected. This is the default
108 if ``FVP_CLUSTER_COUNT`` > 2.
109
110- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
111 a single cluster. This option defaults to 4.
112
113- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
114 in the system. This option defaults to 1. Note that the build option
115 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
116
117- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
118
119 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
120 - ``FVP_GICV2`` : The GICv2 only driver is selected
121 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
122
123- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
124 for functions that wait for an arbitrary time length (udelay and mdelay).
125 The default value is 0.
126
127- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
128 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
129 details on HW_CONFIG. By default, this is initialized to a sensible DTS
130 file in ``fdts/`` folder depending on other build options. But some cases,
131 like shifted affinity format for MPIDR, cannot be detected at build time
132 and this option is needed to specify the appropriate DTS file.
133
134- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
135 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is
136 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
137 HW_CONFIG blob instead of the DTS file. This option is useful to override
138 the default HW_CONFIG selected by the build system.
139
140Booting Firmware Update images
141------------------------------
142
143When Firmware Update (FWU) is enabled there are at least 2 new images
144that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
145FWU FIP.
146
147The additional fip images must be loaded with:
148
149::
150
151 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
152 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
153
154The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
155In the same way, the address ns_bl2u_base_address is the value of
156NS_BL2U_BASE.
157
158Booting an EL3 payload
159----------------------
160
161The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
162the secondary CPUs holding pen to work properly. Unfortunately, its reset value
163is undefined on the FVP platform and the FVP platform code doesn't clear it.
164Therefore, one must modify the way the model is normally invoked in order to
165clear the mailbox at start-up.
166
167One way to do that is to create an 8-byte file containing all zero bytes using
168the following command:
169
170.. code:: shell
171
172 dd if=/dev/zero of=mailbox.dat bs=1 count=8
173
174and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
175using the following model parameters:
176
177::
178
179 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
180 --data=mailbox.dat@0x04000000 [Foundation FVP]
181
182To provide the model with the EL3 payload image, the following methods may be
183used:
184
185#. If the EL3 payload is able to execute in place, it may be programmed into
186 flash memory. On Base Cortex and AEM FVPs, the following model parameter
187 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
188 used for the FIP):
189
190 ::
191
192 -C bp.flashloader1.fname="<path-to>/<el3-payload>"
193
194 On Foundation FVP, there is no flash loader component and the EL3 payload
195 may be programmed anywhere in flash using method 3 below.
196
197#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
198 command may be used to load the EL3 payload ELF image over JTAG:
199
200 ::
201
202 load <path-to>/el3-payload.elf
203
204#. The EL3 payload may be pre-loaded in volatile memory using the following
205 model parameters:
206
207 ::
208
209 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
210 --data="<path-to>/<el3-payload>"@address [Foundation FVP]
211
212 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
213 used when building TF-A.
214
215Booting a preloaded kernel image (Base FVP)
216-------------------------------------------
217
218The following example uses a simplified boot flow by directly jumping from the
219TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
220useful if both the kernel and the device tree blob (DTB) are already present in
221memory (like in FVP).
222
223For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
224address ``0x82000000``, the firmware can be built like this:
225
226.. code:: shell
227
Madhukar Pappireddyc0ba2482020-01-10 16:11:18 -0600228 CROSS_COMPILE=aarch64-none-elf- \
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100229 make PLAT=fvp DEBUG=1 \
230 RESET_TO_BL31=1 \
231 ARM_LINUX_KERNEL_AS_BL33=1 \
232 PRELOADED_BL33_BASE=0x80080000 \
233 ARM_PRELOADED_DTB_BASE=0x82000000 \
234 all fip
235
236Now, it is needed to modify the DTB so that the kernel knows the address of the
237ramdisk. The following script generates a patched DTB from the provided one,
238assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
239script assumes that the user is using a ramdisk image prepared for U-Boot, like
240the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
241offset in ``INITRD_START`` has to be removed.
242
243.. code:: bash
244
245 #!/bin/bash
246
247 # Path to the input DTB
248 KERNEL_DTB=<path-to>/<fdt>
249 # Path to the output DTB
250 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
251 # Base address of the ramdisk
252 INITRD_BASE=0x84000000
253 # Path to the ramdisk
254 INITRD=<path-to>/<ramdisk.img>
255
256 # Skip uboot header (64 bytes)
257 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
258 INITRD_SIZE=$(stat -Lc %s ${INITRD})
259 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
260
261 CHOSEN_NODE=$(echo \
262 "/ { \
263 chosen { \
264 linux,initrd-start = <${INITRD_START}>; \
265 linux,initrd-end = <${INITRD_END}>; \
266 }; \
267 };")
268
269 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
270 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
271
272And the FVP binary can be run with the following command:
273
274.. code:: shell
275
276 <path-to>/FVP_Base_AEMv8A-AEMv8A \
277 -C pctl.startup=0.0.0.0 \
278 -C bp.secure_memory=1 \
279 -C cluster0.NUM_CORES=4 \
280 -C cluster1.NUM_CORES=4 \
281 -C cache_state_modelled=1 \
Alexei Fedorovea0424f2020-02-17 13:38:35 +0000282 -C cluster0.cpu0.RVBAR=0x04001000 \
283 -C cluster0.cpu1.RVBAR=0x04001000 \
284 -C cluster0.cpu2.RVBAR=0x04001000 \
285 -C cluster0.cpu3.RVBAR=0x04001000 \
286 -C cluster1.cpu0.RVBAR=0x04001000 \
287 -C cluster1.cpu1.RVBAR=0x04001000 \
288 -C cluster1.cpu2.RVBAR=0x04001000 \
289 -C cluster1.cpu3.RVBAR=0x04001000 \
290 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100291 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
292 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
293 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
294
295Obtaining the Flattened Device Trees
296^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
297
298Depending on the FVP configuration and Linux configuration used, different
299FDT files are required. FDT source files for the Foundation and Base FVPs can
300be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
301a subset of the Base FVP components. For example, the Foundation FVP lacks
302CLCD and MMC support, and has only one CPU cluster.
303
304.. note::
305 It is not recommended to use the FDTs built along the kernel because not
306 all FDTs are available from there.
307
308The dynamic configuration capability is enabled in the firmware for FVPs.
309This means that the firmware can authenticate and load the FDT if present in
310FIP. A default FDT is packaged into FIP during the build based on
311the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
312or ``FVP_HW_CONFIG_DTS`` build options (refer to
313:ref:`build_options_arm_fvp_platform` for details on the options).
314
315- ``fvp-base-gicv2-psci.dts``
316
317 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
318 affinities and with Base memory map configuration.
319
320- ``fvp-base-gicv2-psci-aarch32.dts``
321
322 For use with models such as the Cortex-A32 Base FVPs without shifted
323 affinities and running Linux in AArch32 state with Base memory map
324 configuration.
325
326- ``fvp-base-gicv3-psci.dts``
327
328 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
329 affinities and with Base memory map configuration and Linux GICv3 support.
330
331- ``fvp-base-gicv3-psci-1t.dts``
332
333 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
334 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
335
336- ``fvp-base-gicv3-psci-dynamiq.dts``
337
338 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
339 single cluster, single threaded CPUs, Base memory map configuration and Linux
340 GICv3 support.
341
342- ``fvp-base-gicv3-psci-aarch32.dts``
343
344 For use with models such as the Cortex-A32 Base FVPs without shifted
345 affinities and running Linux in AArch32 state with Base memory map
346 configuration and Linux GICv3 support.
347
348- ``fvp-foundation-gicv2-psci.dts``
349
350 For use with Foundation FVP with Base memory map configuration.
351
352- ``fvp-foundation-gicv3-psci.dts``
353
354 (Default) For use with Foundation FVP with Base memory map configuration
355 and Linux GICv3 support.
356
357
358Running on the Foundation FVP with reset to BL1 entrypoint
359^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
360
361The following ``Foundation_Platform`` parameters should be used to boot Linux with
3624 CPUs using the AArch64 build of TF-A.
363
364.. code:: shell
365
366 <path-to>/Foundation_Platform \
367 --cores=4 \
368 --arm-v8.0 \
369 --secure-memory \
370 --visualization \
371 --gicv3 \
372 --data="<path-to>/<bl1-binary>"@0x0 \
373 --data="<path-to>/<FIP-binary>"@0x08000000 \
374 --data="<path-to>/<kernel-binary>"@0x80080000 \
375 --data="<path-to>/<ramdisk-binary>"@0x84000000
376
377Notes:
378
379- BL1 is loaded at the start of the Trusted ROM.
380- The Firmware Image Package is loaded at the start of NOR FLASH0.
381- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
382 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
383- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
384 and enable the GICv3 device in the model. Note that without this option,
385 the Foundation FVP defaults to legacy (Versatile Express) memory map which
386 is not supported by TF-A.
387- In order for TF-A to run correctly on the Foundation FVP, the architecture
388 versions must match. The Foundation FVP defaults to the highest v8.x
389 version it supports but the default build for TF-A is for v8.0. To avoid
390 issues either start the Foundation FVP to use v8.0 architecture using the
391 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
392 ``ARM_ARCH_MINOR``.
393
394Running on the AEMv8 Base FVP with reset to BL1 entrypoint
395^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
396
397The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
398with 8 CPUs using the AArch64 build of TF-A.
399
400.. code:: shell
401
402 <path-to>/FVP_Base_RevC-2xAEMv8A \
403 -C pctl.startup=0.0.0.0 \
404 -C bp.secure_memory=1 \
405 -C bp.tzc_400.diagnostics=1 \
406 -C cluster0.NUM_CORES=4 \
407 -C cluster1.NUM_CORES=4 \
408 -C cache_state_modelled=1 \
409 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
410 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
411 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
412 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
413
414.. note::
415 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
416 a specific DTS for all the CPUs to be loaded.
417
418Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
419^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
420
421The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
422with 8 CPUs using the AArch32 build of TF-A.
423
424.. code:: shell
425
426 <path-to>/FVP_Base_AEMv8A-AEMv8A \
427 -C pctl.startup=0.0.0.0 \
428 -C bp.secure_memory=1 \
429 -C bp.tzc_400.diagnostics=1 \
430 -C cluster0.NUM_CORES=4 \
431 -C cluster1.NUM_CORES=4 \
432 -C cache_state_modelled=1 \
433 -C cluster0.cpu0.CONFIG64=0 \
434 -C cluster0.cpu1.CONFIG64=0 \
435 -C cluster0.cpu2.CONFIG64=0 \
436 -C cluster0.cpu3.CONFIG64=0 \
437 -C cluster1.cpu0.CONFIG64=0 \
438 -C cluster1.cpu1.CONFIG64=0 \
439 -C cluster1.cpu2.CONFIG64=0 \
440 -C cluster1.cpu3.CONFIG64=0 \
441 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
442 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
443 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
444 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
445
446Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
447^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
448
449The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
450boot Linux with 8 CPUs using the AArch64 build of TF-A.
451
452.. code:: shell
453
454 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
455 -C pctl.startup=0.0.0.0 \
456 -C bp.secure_memory=1 \
457 -C bp.tzc_400.diagnostics=1 \
458 -C cache_state_modelled=1 \
459 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
460 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
461 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
462 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
463
464Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
465^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
466
467The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
468boot Linux with 4 CPUs using the AArch32 build of TF-A.
469
470.. code:: shell
471
472 <path-to>/FVP_Base_Cortex-A32x4 \
473 -C pctl.startup=0.0.0.0 \
474 -C bp.secure_memory=1 \
475 -C bp.tzc_400.diagnostics=1 \
476 -C cache_state_modelled=1 \
477 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
478 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
479 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
480 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
481
482
483Running on the AEMv8 Base FVP with reset to BL31 entrypoint
484^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
485
486The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
487with 8 CPUs using the AArch64 build of TF-A.
488
489.. code:: shell
490
491 <path-to>/FVP_Base_RevC-2xAEMv8A \
492 -C pctl.startup=0.0.0.0 \
493 -C bp.secure_memory=1 \
494 -C bp.tzc_400.diagnostics=1 \
495 -C cluster0.NUM_CORES=4 \
496 -C cluster1.NUM_CORES=4 \
497 -C cache_state_modelled=1 \
498 -C cluster0.cpu0.RVBAR=0x04010000 \
499 -C cluster0.cpu1.RVBAR=0x04010000 \
500 -C cluster0.cpu2.RVBAR=0x04010000 \
501 -C cluster0.cpu3.RVBAR=0x04010000 \
502 -C cluster1.cpu0.RVBAR=0x04010000 \
503 -C cluster1.cpu1.RVBAR=0x04010000 \
504 -C cluster1.cpu2.RVBAR=0x04010000 \
505 -C cluster1.cpu3.RVBAR=0x04010000 \
506 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
507 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
508 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
509 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
510 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
511 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
512
513Notes:
514
515- If Position Independent Executable (PIE) support is enabled for BL31
516 in this config, it can be loaded at any valid address for execution.
517
518- Since a FIP is not loaded when using BL31 as reset entrypoint, the
519 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
520 parameter is needed to load the individual bootloader images in memory.
521 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
522 Payload. For the same reason, the FDT needs to be compiled from the DT source
523 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
524 parameter.
525
526- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
527 specific DTS for all the CPUs to be loaded.
528
529- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
530 X and Y are the cluster and CPU numbers respectively, is used to set the
531 reset vector for each core.
532
533- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
534 changing the value of
535 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
536 ``BL32_BASE``.
537
538
539Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
540^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
541
542The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
543with 8 CPUs using the AArch32 build of TF-A.
544
545.. code:: shell
546
547 <path-to>/FVP_Base_AEMv8A-AEMv8A \
548 -C pctl.startup=0.0.0.0 \
549 -C bp.secure_memory=1 \
550 -C bp.tzc_400.diagnostics=1 \
551 -C cluster0.NUM_CORES=4 \
552 -C cluster1.NUM_CORES=4 \
553 -C cache_state_modelled=1 \
554 -C cluster0.cpu0.CONFIG64=0 \
555 -C cluster0.cpu1.CONFIG64=0 \
556 -C cluster0.cpu2.CONFIG64=0 \
557 -C cluster0.cpu3.CONFIG64=0 \
558 -C cluster1.cpu0.CONFIG64=0 \
559 -C cluster1.cpu1.CONFIG64=0 \
560 -C cluster1.cpu2.CONFIG64=0 \
561 -C cluster1.cpu3.CONFIG64=0 \
562 -C cluster0.cpu0.RVBAR=0x04002000 \
563 -C cluster0.cpu1.RVBAR=0x04002000 \
564 -C cluster0.cpu2.RVBAR=0x04002000 \
565 -C cluster0.cpu3.RVBAR=0x04002000 \
566 -C cluster1.cpu0.RVBAR=0x04002000 \
567 -C cluster1.cpu1.RVBAR=0x04002000 \
568 -C cluster1.cpu2.RVBAR=0x04002000 \
569 -C cluster1.cpu3.RVBAR=0x04002000 \
570 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
571 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
572 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
573 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
574 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
575
576.. note::
577 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
578 It should match the address programmed into the RVBAR register as well.
579
580Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
581^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
582
583The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
584boot Linux with 8 CPUs using the AArch64 build of TF-A.
585
586.. code:: shell
587
588 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
589 -C pctl.startup=0.0.0.0 \
590 -C bp.secure_memory=1 \
591 -C bp.tzc_400.diagnostics=1 \
592 -C cache_state_modelled=1 \
593 -C cluster0.cpu0.RVBARADDR=0x04010000 \
594 -C cluster0.cpu1.RVBARADDR=0x04010000 \
595 -C cluster0.cpu2.RVBARADDR=0x04010000 \
596 -C cluster0.cpu3.RVBARADDR=0x04010000 \
597 -C cluster1.cpu0.RVBARADDR=0x04010000 \
598 -C cluster1.cpu1.RVBARADDR=0x04010000 \
599 -C cluster1.cpu2.RVBARADDR=0x04010000 \
600 -C cluster1.cpu3.RVBARADDR=0x04010000 \
601 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
602 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
603 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
604 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
605 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
606 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
607
608Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
609^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
610
611The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
612boot Linux with 4 CPUs using the AArch32 build of TF-A.
613
614.. code:: shell
615
616 <path-to>/FVP_Base_Cortex-A32x4 \
617 -C pctl.startup=0.0.0.0 \
618 -C bp.secure_memory=1 \
619 -C bp.tzc_400.diagnostics=1 \
620 -C cache_state_modelled=1 \
621 -C cluster0.cpu0.RVBARADDR=0x04002000 \
622 -C cluster0.cpu1.RVBARADDR=0x04002000 \
623 -C cluster0.cpu2.RVBARADDR=0x04002000 \
624 -C cluster0.cpu3.RVBARADDR=0x04002000 \
625 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
626 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
627 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
628 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
629 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
630
631--------------
632
Imre Kisf05a1622020-02-27 15:05:03 +0100633*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100634
635.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
636.. _Arm's website: `FVP models`_
637.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
638.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
639.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms