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git01.mediatek.com / filogic / atf / 03d8749be47cac6e1587aa2706e17cfc8bbd47d4 / . / plat / arm / board / fvp / include / fconf_hw_config_getter.h
blob: b7a124726a04f9236c6e742194dddb05b7580e1a [file] [log] [blame]
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600[diff] [blame]1/*
AlexeiFedorov334d2352022-12-29 15:57:40 +0000[diff] [blame]2 * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef FCONF_HW_CONFIG_GETTER_H
8#define FCONF_HW_CONFIG_GETTER_H
9
10#include <lib/fconf/fconf.h>
AlexeiFedorov334d2352022-12-29 15:57:40 +0000[diff] [blame]11#include <services/rmm_core_manifest.h>
12
13#include <plat/arm/common/arm_def.h>
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600[diff] [blame]14
15/* Hardware Config related getter */
16#define hw_config__gicv3_config_getter(prop) gicv3_config.prop
Madhukar Pappireddy26b945c2019-12-27 12:02:34 -0600[diff] [blame]17#define hw_config__topology_getter(prop) soc_topology.prop
Madhukar Pappireddy361c1b32020-03-24 10:03:34 -0500[diff] [blame]18#define hw_config__uart_serial_config_getter(prop) uart_serial_config.prop
laurenw-armfc3e7a22020-02-06 11:42:18 -0600[diff] [blame]19#define hw_config__cpu_timer_getter(prop) cpu_timer.prop
AlexeiFedorov334d2352022-12-29 15:57:40 +0000[diff] [blame]20#define hw_config__dram_layout_getter(prop) dram_layout.prop
Madhukar Pappireddy361c1b32020-03-24 10:03:34 -0500[diff] [blame]21
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600[diff] [blame]22struct gicv3_config_t {
laurenw-armdc5e9a22020-05-12 10:58:11 -0500[diff] [blame]23 uint64_t gicd_base;
24 uint64_t gicr_base;
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600[diff] [blame]25};
26
Madhukar Pappireddy26b945c2019-12-27 12:02:34 -0600[diff] [blame]27struct hw_topology_t {
28 uint32_t plat_cluster_count;
29 uint32_t cluster_cpu_count;
30 uint32_t plat_cpu_count;
31 uint32_t plat_max_pwr_level;
32};
33
Madhukar Pappireddy361c1b32020-03-24 10:03:34 -0500[diff] [blame]34struct uart_serial_config_t {
35 uint64_t uart_base;
36 uint32_t uart_clk;
37};
38
laurenw-armfc3e7a22020-02-06 11:42:18 -0600[diff] [blame]39struct cpu_timer_t {
40 uint32_t clock_freq;
41};
42
AlexeiFedorov334d2352022-12-29 15:57:40 +0000[diff] [blame]43struct ns_dram_layout {
44 uint64_t num_banks;
45 struct ns_dram_bank dram_bank[ARM_DRAM_NUM_BANKS];
46};
47
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600[diff] [blame]48int fconf_populate_gicv3_config(uintptr_t config);
Madhukar Pappireddy26b945c2019-12-27 12:02:34 -0600[diff] [blame]49int fconf_populate_topology(uintptr_t config);
Madhukar Pappireddy361c1b32020-03-24 10:03:34 -0500[diff] [blame]50int fconf_populate_uart_config(uintptr_t config);
laurenw-armfc3e7a22020-02-06 11:42:18 -0600[diff] [blame]51int fconf_populate_cpu_timer(uintptr_t config);
AlexeiFedorov334d2352022-12-29 15:57:40 +0000[diff] [blame]52int fconf_populate_dram_layout(uintptr_t config);
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600[diff] [blame]53
54extern struct gicv3_config_t gicv3_config;
Madhukar Pappireddy26b945c2019-12-27 12:02:34 -0600[diff] [blame]55extern struct hw_topology_t soc_topology;
Madhukar Pappireddy361c1b32020-03-24 10:03:34 -0500[diff] [blame]56extern struct uart_serial_config_t uart_serial_config;
laurenw-armfc3e7a22020-02-06 11:42:18 -0600[diff] [blame]57extern struct cpu_timer_t cpu_timer;
AlexeiFedorov334d2352022-12-29 15:57:40 +0000[diff] [blame]58extern struct ns_dram_layout dram_layout;
59
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600[diff] [blame]60#endif /* FCONF_HW_CONFIG_GETTER_H */