| Ard Biesheuvel | c0415c6 | 2018-12-29 19:44:35 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
| 11 | #include <bl31/ehf.h> |
| 12 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 13 | #include <services/secure_partition.h> |
| 14 | |
| 15 | static const mmap_region_t plat_arm_secure_partition_mmap[] = { |
| 16 | PLAT_SQ_FLASH_MMAP, |
| 17 | PLAT_SQ_UART1_MMAP, |
| 18 | PLAT_SQ_PERIPH_MMAP, |
| 19 | PLAT_SQ_SP_IMAGE_MMAP, |
| 20 | PLAT_SP_IMAGE_NS_BUF_MMAP, |
| 21 | PLAT_SQ_SP_IMAGE_RW_MMAP, |
| 22 | PLAT_SPM_SPM_BUF_EL0_MMAP, |
| 23 | {0} |
| 24 | }; |
| 25 | |
| 26 | /* |
| 27 | * Boot information passed to a secure partition during initialisation. Linear |
| 28 | * indices in MP information will be filled at runtime. |
| 29 | */ |
| 30 | static secure_partition_mp_info_t sp_mp_info[] = { |
| 31 | {0x80000000, 0}, {0x80000001, 0}, {0x80000100, 0}, {0x80000101, 0}, |
| 32 | {0x80000200, 0}, {0x80000201, 0}, {0x80000300, 0}, {0x80000301, 0}, |
| 33 | {0x80000400, 0}, {0x80000401, 0}, {0x80000500, 0}, {0x80000501, 0}, |
| 34 | {0x80000600, 0}, {0x80000601, 0}, {0x80000700, 0}, {0x80000701, 0}, |
| 35 | {0x80000800, 0}, {0x80000801, 0}, {0x80000900, 0}, {0x80000901, 0}, |
| 36 | {0x80000a00, 0}, {0x80000a01, 0}, {0x80000b00, 0}, {0x80000b01, 0}, |
| 37 | }; |
| 38 | |
| 39 | const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { |
| 40 | .h.type = PARAM_SP_IMAGE_BOOT_INFO, |
| 41 | .h.version = VERSION_1, |
| 42 | .h.size = sizeof(secure_partition_boot_info_t), |
| 43 | .h.attr = 0, |
| 44 | .sp_mem_base = BL32_BASE, |
| 45 | .sp_mem_limit = BL32_LIMIT, |
| 46 | .sp_image_base = BL32_BASE, |
| 47 | .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, |
| 48 | .sp_heap_base = PLAT_SQ_SP_HEAP_BASE, |
| 49 | .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, |
| 50 | .sp_shared_buf_base = PLAT_SPM_BUF_BASE, |
| 51 | .sp_image_size = PLAT_SQ_SP_IMAGE_SIZE, |
| 52 | .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, |
| 53 | .sp_heap_size = PLAT_SQ_SP_HEAP_SIZE, |
| 54 | .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, |
| 55 | .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, |
| 56 | .num_sp_mem_regions = PLAT_SP_IMAGE_NUM_MEM_REGIONS, |
| 57 | .num_cpus = PLATFORM_CORE_COUNT, |
| 58 | .mp_info = sp_mp_info, |
| 59 | }; |
| 60 | |
| 61 | const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) |
| 62 | { |
| 63 | return plat_arm_secure_partition_mmap; |
| 64 | } |
| 65 | |
| 66 | const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( |
| 67 | void *cookie) |
| 68 | { |
| 69 | return &plat_arm_secure_partition_boot_info; |
| 70 | } |
| 71 | |
| 72 | static ehf_pri_desc_t sq_exceptions[] = { |
| 73 | EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI), |
| 74 | }; |
| 75 | EHF_REGISTER_PRIORITIES(sq_exceptions, ARRAY_SIZE(sq_exceptions), PLAT_PRI_BITS); |