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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Roberto Vargas2ca18d92018-02-12 12:36:17 +00002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
9#include <common/debug.h>
10#include <drivers/arm/tzc400.h>
11
Roberto Vargas2ca18d92018-02-12 12:36:17 +000012#include <plat_arm.h>
Dan Handley9df48042015-03-19 18:58:55 +000013
14/* Weak definitions may be overridden in specific ARM standard platform */
15#pragma weak plat_arm_security_setup
16
17
18/*******************************************************************************
19 * Initialize the TrustZone Controller for ARM standard platforms.
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000020 * When booting an EL3 payload, this is simplified: we configure region 0 with
21 * secure access only and do not enable any other region.
Dan Handley9df48042015-03-19 18:58:55 +000022 ******************************************************************************/
Summer Qin5ce394c2018-03-12 11:28:26 +080023void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions)
Dan Handley9df48042015-03-19 18:58:55 +000024{
Summer Qin5ce394c2018-03-12 11:28:26 +080025#ifndef EL3_PAYLOAD_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010026 unsigned int region_index = 1U;
Summer Qin5ce394c2018-03-12 11:28:26 +080027 const arm_tzc_regions_info_t *p;
28 const arm_tzc_regions_info_t init_tzc_regions[] = {
29 ARM_TZC_REGIONS_DEF,
30 {0}
31 };
32#endif
33
Dan Handley9df48042015-03-19 18:58:55 +000034 INFO("Configuring TrustZone Controller\n");
35
Soby Mathew9c708b52016-02-26 14:23:19 +000036 tzc400_init(PLAT_ARM_TZC_BASE);
Dan Handley9df48042015-03-19 18:58:55 +000037
38 /* Disable filters. */
Soby Mathew9c708b52016-02-26 14:23:19 +000039 tzc400_disable_filters();
Dan Handley9df48042015-03-19 18:58:55 +000040
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000041#ifndef EL3_PAYLOAD_BASE
Summer Qin5ce394c2018-03-12 11:28:26 +080042 if (tzc_regions == NULL)
43 p = init_tzc_regions;
44 else
45 p = tzc_regions;
Soby Mathew7e4d6652017-05-10 11:50:30 +010046
Dan Handley9df48042015-03-19 18:58:55 +000047 /* Region 0 set to no access by default */
Soby Mathew9c708b52016-02-26 14:23:19 +000048 tzc400_configure_region0(TZC_REGION_S_NONE, 0);
Dan Handley9df48042015-03-19 18:58:55 +000049
Summer Qin5ce394c2018-03-12 11:28:26 +080050 /* Rest Regions set according to tzc_regions array */
51 for (; p->base != 0ULL; p++) {
52 tzc400_configure_region(PLAT_ARM_TZC_FILTERS, region_index,
53 p->base, p->end, p->sec_attr, p->nsaid_permissions);
54 region_index++;
55 }
Dan Handley9df48042015-03-19 18:58:55 +000056
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010057 INFO("Total %u regions set.\n", region_index);
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000058
59#else /* if defined(EL3_PAYLOAD_BASE) */
60
Soby Mathew15b149e2017-11-13 08:29:45 +000061 /* Allow Secure and Non-secure access to DRAM for EL3 payloads */
62 tzc400_configure_region0(TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS);
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000063
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000064#endif /* EL3_PAYLOAD_BASE */
Dan Handley9df48042015-03-19 18:58:55 +000065
66 /*
67 * Raise an exception if a NS device tries to access secure memory
68 * TODO: Add interrupt handling support.
69 */
Soby Mathew9c708b52016-02-26 14:23:19 +000070 tzc400_set_action(TZC_ACTION_ERR);
Dan Handley9df48042015-03-19 18:58:55 +000071
72 /* Enable filters. */
Soby Mathew9c708b52016-02-26 14:23:19 +000073 tzc400_enable_filters();
Dan Handley9df48042015-03-19 18:58:55 +000074}
75
76void plat_arm_security_setup(void)
77{
Summer Qin5ce394c2018-03-12 11:28:26 +080078 arm_tzc400_setup(NULL);
Dan Handley9df48042015-03-19 18:58:55 +000079}