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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautier1a3fc9f2019-01-17 14:35:22 +01002 * Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef STM32MP1_RCC_H
8#define STM32MP1_RCC_H
Yann Gautier4b0c72a2018-07-16 10:54:09 +02009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020011
12#define RCC_TZCR U(0x00)
13#define RCC_OCENSETR U(0x0C)
14#define RCC_OCENCLRR U(0x10)
15#define RCC_HSICFGR U(0x18)
16#define RCC_CSICFGR U(0x1C)
17#define RCC_MPCKSELR U(0x20)
18#define RCC_ASSCKSELR U(0x24)
19#define RCC_RCK12SELR U(0x28)
20#define RCC_MPCKDIVR U(0x2C)
21#define RCC_AXIDIVR U(0x30)
22#define RCC_APB4DIVR U(0x3C)
23#define RCC_APB5DIVR U(0x40)
24#define RCC_RTCDIVR U(0x44)
25#define RCC_MSSCKSELR U(0x48)
26#define RCC_PLL1CR U(0x80)
27#define RCC_PLL1CFGR1 U(0x84)
28#define RCC_PLL1CFGR2 U(0x88)
29#define RCC_PLL1FRACR U(0x8C)
30#define RCC_PLL1CSGR U(0x90)
31#define RCC_PLL2CR U(0x94)
32#define RCC_PLL2CFGR1 U(0x98)
33#define RCC_PLL2CFGR2 U(0x9C)
34#define RCC_PLL2FRACR U(0xA0)
35#define RCC_PLL2CSGR U(0xA4)
36#define RCC_I2C46CKSELR U(0xC0)
37#define RCC_SPI6CKSELR U(0xC4)
38#define RCC_UART1CKSELR U(0xC8)
39#define RCC_RNG1CKSELR U(0xCC)
40#define RCC_CPERCKSELR U(0xD0)
41#define RCC_STGENCKSELR U(0xD4)
42#define RCC_DDRITFCR U(0xD8)
43#define RCC_MP_BOOTCR U(0x100)
44#define RCC_MP_SREQSETR U(0x104)
45#define RCC_MP_SREQCLRR U(0x108)
46#define RCC_MP_GCR U(0x10C)
47#define RCC_MP_APRSTCR U(0x110)
48#define RCC_MP_APRSTSR U(0x114)
49#define RCC_BDCR U(0x140)
50#define RCC_RDLSICR U(0x144)
51#define RCC_APB4RSTSETR U(0x180)
52#define RCC_APB4RSTCLRR U(0x184)
53#define RCC_APB5RSTSETR U(0x188)
54#define RCC_APB5RSTCLRR U(0x18C)
55#define RCC_AHB5RSTSETR U(0x190)
56#define RCC_AHB5RSTCLRR U(0x194)
57#define RCC_AHB6RSTSETR U(0x198)
58#define RCC_AHB6RSTCLRR U(0x19C)
59#define RCC_TZAHB6RSTSETR U(0x1A0)
60#define RCC_TZAHB6RSTCLRR U(0x1A4)
61#define RCC_MP_APB4ENSETR U(0x200)
62#define RCC_MP_APB4ENCLRR U(0x204)
63#define RCC_MP_APB5ENSETR U(0x208)
64#define RCC_MP_APB5ENCLRR U(0x20C)
65#define RCC_MP_AHB5ENSETR U(0x210)
66#define RCC_MP_AHB5ENCLRR U(0x214)
67#define RCC_MP_AHB6ENSETR U(0x218)
68#define RCC_MP_AHB6ENCLRR U(0x21C)
69#define RCC_MP_TZAHB6ENSETR U(0x220)
70#define RCC_MP_TZAHB6ENCLRR U(0x224)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +010071#define RCC_MC_APB4ENSETR U(0x280)
72#define RCC_MC_APB4ENCLRR U(0x284)
73#define RCC_MC_APB5ENSETR U(0x288)
74#define RCC_MC_APB5ENCLRR U(0x28C)
75#define RCC_MC_AHB5ENSETR U(0x290)
76#define RCC_MC_AHB5ENCLRR U(0x294)
77#define RCC_MC_AHB6ENSETR U(0x298)
78#define RCC_MC_AHB6ENCLRR U(0x29C)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020079#define RCC_MP_APB4LPENSETR U(0x300)
80#define RCC_MP_APB4LPENCLRR U(0x304)
81#define RCC_MP_APB5LPENSETR U(0x308)
82#define RCC_MP_APB5LPENCLRR U(0x30C)
83#define RCC_MP_AHB5LPENSETR U(0x310)
84#define RCC_MP_AHB5LPENCLRR U(0x314)
85#define RCC_MP_AHB6LPENSETR U(0x318)
86#define RCC_MP_AHB6LPENCLRR U(0x31C)
87#define RCC_MP_TZAHB6LPENSETR U(0x320)
88#define RCC_MP_TZAHB6LPENCLRR U(0x324)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +010089#define RCC_MC_APB4LPENSETR U(0x380)
90#define RCC_MC_APB4LPENCLRR U(0x384)
91#define RCC_MC_APB5LPENSETR U(0x388)
92#define RCC_MC_APB5LPENCLRR U(0x38C)
93#define RCC_MC_AHB5LPENSETR U(0x390)
94#define RCC_MC_AHB5LPENCLRR U(0x394)
95#define RCC_MC_AHB6LPENSETR U(0x398)
96#define RCC_MC_AHB6LPENCLRR U(0x39C)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020097#define RCC_BR_RSTSCLRR U(0x400)
98#define RCC_MP_GRSTCSETR U(0x404)
99#define RCC_MP_RSTSCLRR U(0x408)
100#define RCC_MP_IWDGFZSETR U(0x40C)
101#define RCC_MP_IWDGFZCLRR U(0x410)
102#define RCC_MP_CIER U(0x414)
103#define RCC_MP_CIFR U(0x418)
104#define RCC_PWRLPDLYCR U(0x41C)
105#define RCC_MP_RSTSSETR U(0x420)
106#define RCC_MCO1CFGR U(0x800)
107#define RCC_MCO2CFGR U(0x804)
108#define RCC_OCRDYR U(0x808)
109#define RCC_DBGCFGR U(0x80C)
110#define RCC_RCK3SELR U(0x820)
111#define RCC_RCK4SELR U(0x824)
112#define RCC_TIMG1PRER U(0x828)
113#define RCC_TIMG2PRER U(0x82C)
114#define RCC_APB1DIVR U(0x834)
115#define RCC_APB2DIVR U(0x838)
116#define RCC_APB3DIVR U(0x83C)
117#define RCC_PLL3CR U(0x880)
118#define RCC_PLL3CFGR1 U(0x884)
119#define RCC_PLL3CFGR2 U(0x888)
120#define RCC_PLL3FRACR U(0x88C)
121#define RCC_PLL3CSGR U(0x890)
122#define RCC_PLL4CR U(0x894)
123#define RCC_PLL4CFGR1 U(0x898)
124#define RCC_PLL4CFGR2 U(0x89C)
125#define RCC_PLL4FRACR U(0x8A0)
126#define RCC_PLL4CSGR U(0x8A4)
127#define RCC_I2C12CKSELR U(0x8C0)
128#define RCC_I2C35CKSELR U(0x8C4)
129#define RCC_SAI1CKSELR U(0x8C8)
130#define RCC_SAI2CKSELR U(0x8CC)
131#define RCC_SAI3CKSELR U(0x8D0)
132#define RCC_SAI4CKSELR U(0x8D4)
133#define RCC_SPI2S1CKSELR U(0x8D8)
134#define RCC_SPI2S23CKSELR U(0x8DC)
135#define RCC_SPI45CKSELR U(0x8E0)
136#define RCC_UART6CKSELR U(0x8E4)
137#define RCC_UART24CKSELR U(0x8E8)
138#define RCC_UART35CKSELR U(0x8EC)
139#define RCC_UART78CKSELR U(0x8F0)
140#define RCC_SDMMC12CKSELR U(0x8F4)
141#define RCC_SDMMC3CKSELR U(0x8F8)
142#define RCC_ETHCKSELR U(0x8FC)
143#define RCC_QSPICKSELR U(0x900)
144#define RCC_FMCCKSELR U(0x904)
145#define RCC_FDCANCKSELR U(0x90C)
146#define RCC_SPDIFCKSELR U(0x914)
147#define RCC_CECCKSELR U(0x918)
148#define RCC_USBCKSELR U(0x91C)
149#define RCC_RNG2CKSELR U(0x920)
150#define RCC_DSICKSELR U(0x924)
151#define RCC_ADCCKSELR U(0x928)
152#define RCC_LPTIM45CKSELR U(0x92C)
153#define RCC_LPTIM23CKSELR U(0x930)
154#define RCC_LPTIM1CKSELR U(0x934)
155#define RCC_APB1RSTSETR U(0x980)
156#define RCC_APB1RSTCLRR U(0x984)
157#define RCC_APB2RSTSETR U(0x988)
158#define RCC_APB2RSTCLRR U(0x98C)
159#define RCC_APB3RSTSETR U(0x990)
160#define RCC_APB3RSTCLRR U(0x994)
161#define RCC_AHB2RSTSETR U(0x998)
162#define RCC_AHB2RSTCLRR U(0x99C)
163#define RCC_AHB3RSTSETR U(0x9A0)
164#define RCC_AHB3RSTCLRR U(0x9A4)
165#define RCC_AHB4RSTSETR U(0x9A8)
166#define RCC_AHB4RSTCLRR U(0x9AC)
167#define RCC_MP_APB1ENSETR U(0xA00)
168#define RCC_MP_APB1ENCLRR U(0xA04)
169#define RCC_MP_APB2ENSETR U(0xA08)
170#define RCC_MP_APB2ENCLRR U(0xA0C)
171#define RCC_MP_APB3ENSETR U(0xA10)
172#define RCC_MP_APB3ENCLRR U(0xA14)
173#define RCC_MP_AHB2ENSETR U(0xA18)
174#define RCC_MP_AHB2ENCLRR U(0xA1C)
175#define RCC_MP_AHB3ENSETR U(0xA20)
176#define RCC_MP_AHB3ENCLRR U(0xA24)
177#define RCC_MP_AHB4ENSETR U(0xA28)
178#define RCC_MP_AHB4ENCLRR U(0xA2C)
179#define RCC_MP_MLAHBENSETR U(0xA38)
180#define RCC_MP_MLAHBENCLRR U(0xA3C)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100181#define RCC_MC_APB1ENSETR U(0xA80)
182#define RCC_MC_APB1ENCLRR U(0xA84)
183#define RCC_MC_APB2ENSETR U(0xA88)
184#define RCC_MC_APB2ENCLRR U(0xA8C)
185#define RCC_MC_APB3ENSETR U(0xA90)
186#define RCC_MC_APB3ENCLRR U(0xA94)
187#define RCC_MC_AHB2ENSETR U(0xA98)
188#define RCC_MC_AHB2ENCLRR U(0xA9C)
189#define RCC_MC_AHB3ENSETR U(0xAA0)
190#define RCC_MC_AHB3ENCLRR U(0xAA4)
191#define RCC_MC_AHB4ENSETR U(0xAA8)
192#define RCC_MC_AHB4ENCLRR U(0xAAC)
193#define RCC_MC_AXIMENSETR U(0xAB0)
194#define RCC_MC_AXIMENCLRR U(0xAB4)
195#define RCC_MC_MLAHBENSETR U(0xAB8)
196#define RCC_MC_MLAHBENCLRR U(0xABC)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200197#define RCC_MP_APB1LPENSETR U(0xB00)
198#define RCC_MP_APB1LPENCLRR U(0xB04)
199#define RCC_MP_APB2LPENSETR U(0xB08)
200#define RCC_MP_APB2LPENCLRR U(0xB0C)
201#define RCC_MP_APB3LPENSETR U(0xB10)
202#define RCC_MP_APB3LPENCLRR U(0xB14)
203#define RCC_MP_AHB2LPENSETR U(0xB18)
204#define RCC_MP_AHB2LPENCLRR U(0xB1C)
205#define RCC_MP_AHB3LPENSETR U(0xB20)
206#define RCC_MP_AHB3LPENCLRR U(0xB24)
207#define RCC_MP_AHB4LPENSETR U(0xB28)
208#define RCC_MP_AHB4LPENCLRR U(0xB2C)
209#define RCC_MP_AXIMLPENSETR U(0xB30)
210#define RCC_MP_AXIMLPENCLRR U(0xB34)
211#define RCC_MP_MLAHBLPENSETR U(0xB38)
212#define RCC_MP_MLAHBLPENCLRR U(0xB3C)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100213#define RCC_MC_APB1LPENSETR U(0xB80)
214#define RCC_MC_APB1LPENCLRR U(0xB84)
215#define RCC_MC_APB2LPENSETR U(0xB88)
216#define RCC_MC_APB2LPENCLRR U(0xB8C)
217#define RCC_MC_APB3LPENSETR U(0xB90)
218#define RCC_MC_APB3LPENCLRR U(0xB94)
219#define RCC_MC_AHB2LPENSETR U(0xB98)
220#define RCC_MC_AHB2LPENCLRR U(0xB9C)
221#define RCC_MC_AHB3LPENSETR U(0xBA0)
222#define RCC_MC_AHB3LPENCLRR U(0xBA4)
223#define RCC_MC_AHB4LPENSETR U(0xBA8)
224#define RCC_MC_AHB4LPENCLRR U(0xBAC)
225#define RCC_MC_AXIMLPENSETR U(0xBB0)
226#define RCC_MC_AXIMLPENCLRR U(0xBB4)
227#define RCC_MC_MLAHBLPENSETR U(0xBB8)
228#define RCC_MC_MLAHBLPENCLRR U(0xBBC)
229#define RCC_MC_RSTSCLRR U(0xC00)
230#define RCC_MC_CIER U(0xC14)
231#define RCC_MC_CIFR U(0xC18)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200232#define RCC_VERR U(0xFF4)
233#define RCC_IDR U(0xFF8)
234#define RCC_SIDR U(0xFFC)
235
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100236#define RCC_OFFSET_MASK GENMASK(11, 0)
237
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200238/* Values for RCC_TZCR register */
239#define RCC_TZCR_TZEN BIT(0)
240
241/* Used for most of RCC_<x>SELR registers */
242#define RCC_SELR_SRC_MASK GENMASK(2, 0)
243#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0)
244#define RCC_SELR_SRCRDY BIT(31)
245
246/* Values of RCC_MPCKSELR register */
247#define RCC_MPCKSELR_HSI 0x00000000
248#define RCC_MPCKSELR_HSE 0x00000001
249#define RCC_MPCKSELR_PLL 0x00000002
250#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003
251
252/* Values of RCC_ASSCKSELR register */
253#define RCC_ASSCKSELR_HSI 0x00000000
254#define RCC_ASSCKSELR_HSE 0x00000001
255#define RCC_ASSCKSELR_PLL 0x00000002
256
257/* Values of RCC_MSSCKSELR register */
258#define RCC_MSSCKSELR_HSI 0x00000000
259#define RCC_MSSCKSELR_HSE 0x00000001
260#define RCC_MSSCKSELR_CSI 0x00000002
261#define RCC_MSSCKSELR_PLL 0x00000003
262
263/* Values of RCC_CPERCKSELR register */
264#define RCC_CPERCKSELR_HSI 0x00000000
265#define RCC_CPERCKSELR_CSI 0x00000001
266#define RCC_CPERCKSELR_HSE 0x00000002
267
268/* Used for most of DIVR register: max div for RTC */
269#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
270#define RCC_DIVR_DIVRDY BIT(31)
271
272/* Masks for specific DIVR registers */
273#define RCC_APBXDIV_MASK GENMASK(2, 0)
274#define RCC_MPUDIV_MASK GENMASK(2, 0)
275#define RCC_AXIDIV_MASK GENMASK(2, 0)
276
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100277/* Used for TIMER Prescaler */
278#define RCC_TIMGXPRER_TIMGXPRE BIT(0)
279
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200280/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
281#define RCC_MP_ENCLRR_OFFSET U(4)
282
283/* Fields of RCC_BDCR register */
284#define RCC_BDCR_LSEON BIT(0)
285#define RCC_BDCR_LSEBYP BIT(1)
286#define RCC_BDCR_LSERDY BIT(2)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100287#define RCC_BDCR_DIGBYP BIT(3)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200288#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
289#define RCC_BDCR_LSEDRV_SHIFT 4
290#define RCC_BDCR_LSECSSON BIT(8)
291#define RCC_BDCR_RTCCKEN BIT(20)
292#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
293#define RCC_BDCR_RTCSRC_SHIFT 16
294#define RCC_BDCR_VSWRST BIT(31)
295
296/* Fields of RCC_RDLSICR register */
297#define RCC_RDLSICR_LSION BIT(0)
298#define RCC_RDLSICR_LSIRDY BIT(1)
299
300/* Used for all RCC_PLL<n>CR registers */
301#define RCC_PLLNCR_PLLON BIT(0)
302#define RCC_PLLNCR_PLLRDY BIT(1)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100303#define RCC_PLLNCR_SSCG_CTRL BIT(2)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200304#define RCC_PLLNCR_DIVPEN BIT(4)
305#define RCC_PLLNCR_DIVQEN BIT(5)
306#define RCC_PLLNCR_DIVREN BIT(6)
307#define RCC_PLLNCR_DIVEN_SHIFT 4
308
309/* Used for all RCC_PLL<n>CFGR1 registers */
310#define RCC_PLLNCFGR1_DIVM_SHIFT 16
311#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
312#define RCC_PLLNCFGR1_DIVN_SHIFT 0
313#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
314/* Only for PLL3 and PLL4 */
315#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
316#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
317
318/* Used for all RCC_PLL<n>CFGR2 registers */
319#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
320#define RCC_PLLNCFGR2_DIVP_SHIFT 0
321#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
322#define RCC_PLLNCFGR2_DIVQ_SHIFT 8
323#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
324#define RCC_PLLNCFGR2_DIVR_SHIFT 16
325#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
326
327/* Used for all RCC_PLL<n>FRACR registers */
328#define RCC_PLLNFRACR_FRACV_SHIFT 3
329#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
330#define RCC_PLLNFRACR_FRACLE BIT(16)
331
332/* Used for all RCC_PLL<n>CSGR registers */
333#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
334#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
335#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
336#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
337#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
338#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
339
340/* Used for RCC_OCENSETR and RCC_OCENCLRR registers */
341#define RCC_OCENR_HSION BIT(0)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100342#define RCC_OCENR_HSIKERON BIT(1)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200343#define RCC_OCENR_CSION BIT(4)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100344#define RCC_OCENR_CSIKERON BIT(5)
345#define RCC_OCENR_DIGBYP BIT(7)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200346#define RCC_OCENR_HSEON BIT(8)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100347#define RCC_OCENR_HSEKERON BIT(9)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200348#define RCC_OCENR_HSEBYP BIT(10)
349#define RCC_OCENR_HSECSSON BIT(11)
350
351/* Fields of RCC_OCRDYR register */
352#define RCC_OCRDYR_HSIRDY BIT(0)
353#define RCC_OCRDYR_HSIDIVRDY BIT(2)
354#define RCC_OCRDYR_CSIRDY BIT(4)
355#define RCC_OCRDYR_HSERDY BIT(8)
356
357/* Fields of RCC_DDRITFCR register */
358#define RCC_DDRITFCR_DDRC1EN BIT(0)
359#define RCC_DDRITFCR_DDRC1LPEN BIT(1)
360#define RCC_DDRITFCR_DDRC2EN BIT(2)
361#define RCC_DDRITFCR_DDRC2LPEN BIT(3)
362#define RCC_DDRITFCR_DDRPHYCEN BIT(4)
363#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5)
364#define RCC_DDRITFCR_DDRCAPBEN BIT(6)
365#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7)
366#define RCC_DDRITFCR_AXIDCGEN BIT(8)
367#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9)
368#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10)
369#define RCC_DDRITFCR_DDRCAPBRST BIT(14)
370#define RCC_DDRITFCR_DDRCAXIRST BIT(15)
371#define RCC_DDRITFCR_DDRCORERST BIT(16)
372#define RCC_DDRITFCR_DPHYAPBRST BIT(17)
373#define RCC_DDRITFCR_DPHYRST BIT(18)
374#define RCC_DDRITFCR_DPHYCTLRST BIT(19)
375#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
376#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
377#define RCC_DDRITFCR_DDRCKMOD_SSR 0
378#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20)
379#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21)
380#define RCC_DDRITFCR_GSKPCTRL BIT(24)
381
382/* Fields of RCC_HSICFGR register */
383#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100384#define RCC_HSICFGR_HSITRIM_SHIFT 8
385#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8)
386#define RCC_HSICFGR_HSICAL_SHIFT 16
387#define RCC_HSICFGR_HSICAL_MASK GENMASK(27, 16)
388
389/* Fields of RCC_CSICFGR register */
390#define RCC_CSICFGR_CSITRIM_SHIFT 8
391#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8)
392#define RCC_CSICFGR_CSICAL_SHIFT 16
393#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200394
395/* Used for RCC_MCO related operations */
396#define RCC_MCOCFG_MCOON BIT(12)
397#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
398#define RCC_MCOCFG_MCODIV_SHIFT 4
399#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
400
401/* Fields of RCC_DBGCFGR register */
402#define RCC_DBGCFGR_DBGCKEN BIT(8)
403
404/* RCC register fields for reset reasons */
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100405#define RCC_MP_RSTSCLRR_PORRSTF BIT(0)
406#define RCC_MP_RSTSCLRR_BORRSTF BIT(1)
407#define RCC_MP_RSTSCLRR_PADRSTF BIT(2)
408#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3)
409#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4)
410#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6)
411#define RCC_MP_RSTSCLRR_MCSYSRSTF BIT(7)
412#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8)
413#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9)
414#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11)
415#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12)
416#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13)
417#define RCC_MP_RSTSCLRR_MPUP1RSTF BIT(14)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200418
419/* Global Reset Register */
420#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100421#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
422#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200423
424/* Clock Source Interrupt Flag Register */
425#define RCC_MP_CIFR_MASK U(0x110F1F)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100426#define RCC_MP_CIFR_LSIRDYF BIT(0)
427#define RCC_MP_CIFR_LSERDYF BIT(1)
428#define RCC_MP_CIFR_HSIRDYF BIT(2)
429#define RCC_MP_CIFR_HSERDYF BIT(3)
430#define RCC_MP_CIFR_CSIRDYF BIT(4)
431#define RCC_MP_CIFR_PLL1DYF BIT(8)
432#define RCC_MP_CIFR_PLL2DYF BIT(9)
433#define RCC_MP_CIFR_PLL3DYF BIT(10)
434#define RCC_MP_CIFR_PLL4DYF BIT(11)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200435#define RCC_MP_CIFR_WKUPF BIT(20)
436
437/* Stop Request Set Register */
438#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
439#define RCC_MP_SREQSETR_STPREQ_P1 BIT(1)
440
441/* Stop Request Clear Register */
442#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
443#define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1)
444
445/* Values of RCC_UART24CKSELR register */
446#define RCC_UART24CKSELR_HSI 0x00000002
447
448/* Values of RCC_MP_APB1ENSETR register */
449#define RCC_MP_APB1ENSETR_UART4EN BIT(16)
450
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100451/* Values of RCC_MP_APB5ENSETR register */
452#define RCC_MP_APB5ENSETR_SPI6EN BIT(0)
453#define RCC_MP_APB5ENSETR_I2C4EN BIT(2)
454#define RCC_MP_APB5ENSETR_I2C6EN BIT(3)
455#define RCC_MP_APB5ENSETR_USART1EN BIT(4)
456#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8)
457#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15)
458
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200459/* Values of RCC_MP_AHB4ENSETR register */
460#define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6)
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100461#define RCC_MP_AHB4ENSETR_GPIOHEN BIT(7)
462
463/* Values of RCC_MP_AHB5ENSETR register */
464#define RCC_MP_AHB5ENSETR_GPIOZEN BIT(0)
465#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4)
466#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5)
467#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6)
468
469/* Values of RCC_MP_IWDGFZSETR register */
470#define RCC_MP_IWDGFZSETR_IWDG1 BIT(0)
471#define RCC_MP_IWDGFZSETR_IWDG2 BIT(1)
472
473/* Values of RCC_PWRLPDLYCR register */
474#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200475
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000476#endif /* STM32MP1_RCC_H */