blob: 38e1a61e763e987f55a67faae83b5a904f3d42c3 [file] [log] [blame]
Soby Mathew12012dd2015-10-26 14:01:53 +00001/*
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathew12012dd2015-10-26 14:01:53 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew12012dd2015-10-26 14:01:53 +00005 */
6#include <assert.h>
7#include <gic_common.h>
8#include <gicv2.h>
9#include <interrupt_mgmt.h>
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010010#include <platform.h>
Soby Mathew12012dd2015-10-26 14:01:53 +000011
12/*
13 * The following platform GIC functions are weakly defined. They
14 * provide typical implementations that may be re-used by multiple
15 * platforms but may also be overridden by a platform if required.
16 */
17#pragma weak plat_ic_get_pending_interrupt_id
18#pragma weak plat_ic_get_pending_interrupt_type
19#pragma weak plat_ic_acknowledge_interrupt
20#pragma weak plat_ic_get_interrupt_type
21#pragma weak plat_ic_end_of_interrupt
22#pragma weak plat_interrupt_type_to_line
23
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010024#pragma weak plat_ic_get_running_priority
Jeenu Viswambharan522a4652017-09-22 08:32:09 +010025#pragma weak plat_ic_is_spi
26#pragma weak plat_ic_is_ppi
27#pragma weak plat_ic_is_sgi
Jeenu Viswambharan24e70292017-09-22 08:32:09 +010028#pragma weak plat_ic_get_interrupt_active
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +010029#pragma weak plat_ic_enable_interrupt
30#pragma weak plat_ic_disable_interrupt
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +010031#pragma weak plat_ic_set_interrupt_priority
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010032#pragma weak plat_ic_set_interrupt_type
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010033#pragma weak plat_ic_raise_el3_sgi
Jeenu Viswambharandce70b32017-09-22 08:32:09 +010034#pragma weak plat_ic_set_spi_routing
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010035
Soby Mathew12012dd2015-10-26 14:01:53 +000036/*
37 * This function returns the highest priority pending interrupt at
38 * the Interrupt controller
39 */
40uint32_t plat_ic_get_pending_interrupt_id(void)
41{
42 unsigned int id;
43
44 id = gicv2_get_pending_interrupt_id();
45 if (id == GIC_SPURIOUS_INTERRUPT)
46 return INTR_ID_UNAVAILABLE;
47
48 return id;
49}
50
51/*
52 * This function returns the type of the highest priority pending interrupt
53 * at the Interrupt controller. In the case of GICv2, the Highest Priority
54 * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of
55 * the pending interrupt. The type of interrupt depends upon the id value
56 * as follows.
57 * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt
58 * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt.
59 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt
60 * type.
61 */
62uint32_t plat_ic_get_pending_interrupt_type(void)
63{
64 unsigned int id;
65
66 id = gicv2_get_pending_interrupt_type();
67
68 /* Assume that all secure interrupts are S-EL1 interrupts */
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010069 if (id < PENDING_G1_INTID) {
70#if GICV2_G0_FOR_EL3
71 return INTR_TYPE_EL3;
72#else
Soby Mathew12012dd2015-10-26 14:01:53 +000073 return INTR_TYPE_S_EL1;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010074#endif
75 }
Soby Mathew12012dd2015-10-26 14:01:53 +000076
77 if (id == GIC_SPURIOUS_INTERRUPT)
78 return INTR_TYPE_INVAL;
79
80 return INTR_TYPE_NS;
81}
82
83/*
84 * This function returns the highest priority pending interrupt at
85 * the Interrupt controller and indicates to the Interrupt controller
86 * that the interrupt processing has started.
87 */
88uint32_t plat_ic_acknowledge_interrupt(void)
89{
90 return gicv2_acknowledge_interrupt();
91}
92
93/*
94 * This function returns the type of the interrupt `id`, depending on how
95 * the interrupt has been configured in the interrupt controller
96 */
97uint32_t plat_ic_get_interrupt_type(uint32_t id)
98{
99 unsigned int type;
100
101 type = gicv2_get_interrupt_group(id);
102
103 /* Assume that all secure interrupts are S-EL1 interrupts */
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100104 return type == GICV2_INTR_GROUP1 ? INTR_TYPE_NS :
105#if GICV2_G0_FOR_EL3
106 INTR_TYPE_EL3;
107#else
108 INTR_TYPE_S_EL1;
109#endif
Soby Mathew12012dd2015-10-26 14:01:53 +0000110}
111
112/*
113 * This functions is used to indicate to the interrupt controller that
114 * the processing of the interrupt corresponding to the `id` has
115 * finished.
116 */
117void plat_ic_end_of_interrupt(uint32_t id)
118{
119 gicv2_end_of_interrupt(id);
120}
121
122/*
123 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
124 * The interrupt controller knows which pin/line it uses to signal a type of
125 * interrupt. It lets the interrupt management framework determine
126 * for a type of interrupt and security state, which line should be used in the
127 * SCR_EL3 to control its routing to EL3. The interrupt line is represented
128 * as the bit position of the IRQ or FIQ bit in the SCR_EL3.
129 */
130uint32_t plat_interrupt_type_to_line(uint32_t type,
131 uint32_t security_state)
132{
133 assert(type == INTR_TYPE_S_EL1 ||
134 type == INTR_TYPE_EL3 ||
135 type == INTR_TYPE_NS);
136
137 /* Non-secure interrupts are signaled on the IRQ line always */
138 if (type == INTR_TYPE_NS)
139 return __builtin_ctz(SCR_IRQ_BIT);
140
141 /*
142 * Secure interrupts are signaled using the IRQ line if the FIQ is
143 * not enabled else they are signaled using the FIQ line.
144 */
145 return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) :
146 __builtin_ctz(SCR_IRQ_BIT));
147}
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100148
149unsigned int plat_ic_get_running_priority(void)
150{
151 return gicv2_get_running_priority();
152}
Jeenu Viswambharan522a4652017-09-22 08:32:09 +0100153
154int plat_ic_is_spi(unsigned int id)
155{
156 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID);
157}
158
159int plat_ic_is_ppi(unsigned int id)
160{
161 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID);
162}
163
164int plat_ic_is_sgi(unsigned int id)
165{
166 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID);
167}
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100168
169unsigned int plat_ic_get_interrupt_active(unsigned int id)
170{
171 return gicv2_get_interrupt_active(id);
172}
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100173
174void plat_ic_enable_interrupt(unsigned int id)
175{
176 gicv2_enable_interrupt(id);
177}
178
179void plat_ic_disable_interrupt(unsigned int id)
180{
181 gicv2_disable_interrupt(id);
182}
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +0100183
184void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority)
185{
186 gicv2_set_interrupt_priority(id, priority);
187}
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100188
189int plat_ic_has_interrupt_type(unsigned int type)
190{
191 switch (type) {
192#if GICV2_G0_FOR_EL3
193 case INTR_TYPE_EL3:
194#else
195 case INTR_TYPE_S_EL1:
196#endif
197 case INTR_TYPE_NS:
198 return 1;
199 default:
200 return 0;
201 }
202}
203
204void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
205{
206 int gicv2_type = 0;
207
208 /* Map canonical interrupt type to GICv2 type */
209 switch (type) {
210#if GICV2_G0_FOR_EL3
211 case INTR_TYPE_EL3:
212#else
213 case INTR_TYPE_S_EL1:
214#endif
215 gicv2_type = GICV2_INTR_GROUP0;
216 break;
217 case INTR_TYPE_NS:
218 gicv2_type = GICV2_INTR_GROUP1;
219 break;
220 default:
221 assert(0);
222 }
223
224 gicv2_set_interrupt_type(id, gicv2_type);
225}
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100226
227void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
228{
229#if GICV2_G0_FOR_EL3
230 int id;
231
232 /* Target must be a valid MPIDR in the system */
233 id = plat_core_pos_by_mpidr(target);
234 assert(id >= 0);
235
236 /* Verify that this is a secure SGI */
237 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3);
238
239 gicv2_raise_sgi(sgi_num, id);
240#else
241 assert(0);
242#endif
243}
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100244
245void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
246 u_register_t mpidr)
247{
248 int proc_num = 0;
249
250 switch (routing_mode) {
251 case INTR_ROUTING_MODE_PE:
252 proc_num = plat_core_pos_by_mpidr(mpidr);
253 assert(proc_num >= 0);
254 break;
255 case INTR_ROUTING_MODE_ANY:
256 /* Bit mask selecting all 8 CPUs as candidates */
257 proc_num = -1;
258 break;
259 default:
260 assert(0);
261 }
262
263 gicv2_set_spi_routing(id, proc_num);
264}
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100265
266void plat_ic_set_interrupt_pending(unsigned int id)
267{
268 gicv2_set_interrupt_pending(id);
269}
270
271void plat_ic_clear_interrupt_pending(unsigned int id)
272{
273 gicv2_clear_interrupt_pending(id);
274}
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100275
276unsigned int plat_ic_set_priority_mask(unsigned int mask)
277{
278 return gicv2_set_pmr(mask);
279}
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +0100280
281unsigned int plat_ic_get_interrupt_id(unsigned int raw)
282{
283 unsigned int id = (raw & INT_ID_MASK);
284
285 if (id == GIC_SPURIOUS_INTERRUPT)
286 id = INTR_ID_UNAVAILABLE;
287
288 return id;
289}