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Varun Wadekar9f4a7d32018-10-19 11:42:28 -07001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar2909fa32020-01-09 08:52:10 -08003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar9f4a7d32018-10-19 11:42:28 -07004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
Varun Wadekar2909fa32020-01-09 08:52:10 -08008#ifndef TEGRA_GIC_H
9#define TEGRA_GIC_H
Varun Wadekar9f4a7d32018-10-19 11:42:28 -070010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/interrupt_props.h>
Varun Wadekar9f4a7d32018-10-19 11:42:28 -070012
13/*******************************************************************************
14 * Per-CPU struct describing FIQ state to be stored
15 ******************************************************************************/
16typedef struct pcpu_fiq_state {
17 uint64_t elr_el3;
18 uint64_t spsr_el3;
19} pcpu_fiq_state_t;
20
21/*******************************************************************************
22 * Fucntion declarations
23 ******************************************************************************/
24void tegra_gic_cpuif_deactivate(void);
25void tegra_gic_init(void);
26void tegra_gic_pcpu_init(void);
27void tegra_gic_setup(const interrupt_prop_t *interrupt_props,
28 unsigned int interrupt_props_num);
29
Varun Wadekar2909fa32020-01-09 08:52:10 -080030#endif /* TEGRA_GIC_H */