blob: 5f1bb4f28ad1695a3d8f2c032d8c99d32b0f1324 [file] [log] [blame]
Varun Wadekarb5568282016-12-13 18:04:35 -08001/*
Varun Wadekar5a700942019-01-23 16:54:12 -08002 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb5568282016-12-13 18:04:35 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb5568282016-12-13 18:04:35 -08005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef MCE_H
8#define MCE_H
Varun Wadekarb5568282016-12-13 18:04:35 -08009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/mmio.h>
11
Varun Wadekarb5568282016-12-13 18:04:35 -080012#include <tegra_def.h>
13
14/*******************************************************************************
15 * MCE commands
16 ******************************************************************************/
17typedef enum mce_cmd {
Anthony Zhou59fd6152017-03-13 15:34:08 +080018 MCE_CMD_ENTER_CSTATE = 0U,
19 MCE_CMD_UPDATE_CSTATE_INFO = 1U,
20 MCE_CMD_UPDATE_CROSSOVER_TIME = 2U,
21 MCE_CMD_READ_CSTATE_STATS = 3U,
22 MCE_CMD_WRITE_CSTATE_STATS = 4U,
23 MCE_CMD_IS_SC7_ALLOWED = 5U,
24 MCE_CMD_ONLINE_CORE = 6U,
25 MCE_CMD_CC3_CTRL = 7U,
26 MCE_CMD_ECHO_DATA = 8U,
27 MCE_CMD_READ_VERSIONS = 9U,
28 MCE_CMD_ENUM_FEATURES = 10U,
29 MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11U,
30 MCE_CMD_ENUM_READ_MCA = 12U,
31 MCE_CMD_ENUM_WRITE_MCA = 13U,
32 MCE_CMD_ROC_FLUSH_CACHE = 14U,
33 MCE_CMD_ROC_CLEAN_CACHE = 15U,
34 MCE_CMD_ENABLE_LATIC = 16U,
35 MCE_CMD_UNCORE_PERFMON_REQ = 17U,
36 MCE_CMD_MISC_CCPLEX = 18U,
37 MCE_CMD_IS_CCX_ALLOWED = 0xFEU,
38 MCE_CMD_MAX = 0xFFU,
Varun Wadekarb5568282016-12-13 18:04:35 -080039} mce_cmd_t;
40
Anthony Zhou59fd6152017-03-13 15:34:08 +080041#define MCE_CMD_MASK 0xFFU
Varun Wadekarb5568282016-12-13 18:04:35 -080042
43/*******************************************************************************
44 * Timeout value used to powerdown a core
45 ******************************************************************************/
Anthony Zhou59fd6152017-03-13 15:34:08 +080046#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFFU
Varun Wadekarb5568282016-12-13 18:04:35 -080047
48/*******************************************************************************
49 * Struct to prepare UPDATE_CSTATE_INFO request
50 ******************************************************************************/
51typedef struct mce_cstate_info {
52 /* cluster cstate value */
53 uint32_t cluster;
54 /* ccplex cstate value */
55 uint32_t ccplex;
56 /* system cstate value */
57 uint32_t system;
58 /* force system state? */
59 uint8_t system_state_force;
60 /* wake mask value */
61 uint32_t wake_mask;
62 /* update the wake mask? */
63 uint8_t update_wake_mask;
64} mce_cstate_info_t;
65
66/* public interfaces */
Anthony Zhou1ab31402017-03-06 16:06:45 +080067int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
Varun Wadekarb5568282016-12-13 18:04:35 -080068 uint64_t arg2);
69int mce_update_reset_vector(void);
70int mce_update_gsc_videomem(void);
71int mce_update_gsc_tzdram(void);
Varun Wadekarb5568282016-12-13 18:04:35 -080072__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
Anthony Zhou1ab31402017-03-06 16:06:45 +080073void mce_update_cstate_info(const mce_cstate_info_t *cstate);
Varun Wadekarb5568282016-12-13 18:04:35 -080074void mce_verify_firmware_version(void);
75
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000076#endif /* MCE_H */