| Jeenu Viswambharan | d1ff62a | 2018-01-31 10:57:46 +0000 | [diff] [blame] | 1 | /* |
| Balint Dobszay | 5ce2c32 | 2020-01-10 17:16:27 +0100 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. |
| Jeenu Viswambharan | d1ff62a | 2018-01-31 10:57:46 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
| Balint Dobszay | 5ce2c32 | 2020-01-10 17:16:27 +0100 | [diff] [blame] | 9 | #include "fvp-base-gicv3-psci-common.dtsi" |
| Jeenu Viswambharan | d1ff62a | 2018-01-31 10:57:46 +0000 | [diff] [blame] | 10 | |
| 11 | &CPU0 { |
| 12 | reg = <0x0 0x0>; |
| 13 | }; |
| 14 | |
| 15 | &CPU1 { |
| 16 | reg = <0x0 0x100>; |
| 17 | }; |
| 18 | |
| 19 | &CPU2 { |
| 20 | reg = <0x0 0x200>; |
| 21 | }; |
| 22 | |
| 23 | &CPU3 { |
| 24 | reg = <0x0 0x300>; |
| 25 | }; |
| 26 | |
| 27 | &CPU4 { |
| 28 | reg = <0x0 0x400>; |
| 29 | }; |
| 30 | |
| 31 | &CPU5 { |
| 32 | reg = <0x0 0x500>; |
| 33 | }; |
| 34 | |
| 35 | &CPU6 { |
| 36 | reg = <0x0 0x600>; |
| 37 | }; |
| 38 | |
| 39 | &CPU7 { |
| 40 | reg = <0x0 0x700>; |
| 41 | }; |