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Soby Mathew0d786072016-03-24 16:56:29 +00001/*
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathew0d786072016-03-24 16:56:29 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew0d786072016-03-24 16:56:29 +00005 */
6
7#include <arch.h>
8#include <assert.h>
9#include <platform.h>
dp-arm66abfbe2017-01-31 13:01:04 +000010#include <pmf.h>
Soby Mathew0d786072016-03-24 16:56:29 +000011#include <psci.h>
12
dp-arm66abfbe2017-01-31 13:01:04 +000013#if ENABLE_PSCI_STAT && ENABLE_PMF
14#pragma weak plat_psci_stat_accounting_start
15#pragma weak plat_psci_stat_accounting_stop
16#pragma weak plat_psci_stat_get_residency
17
18/* Ticks elapsed in one second by a signal of 1 MHz */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010019#define MHZ_TICKS_PER_SEC 1000000U
dp-arm66abfbe2017-01-31 13:01:04 +000020
Soby Mathew8336f682017-10-16 15:19:31 +010021/* Maximum time-stamp value read from architectural counters */
22#ifdef AARCH32
23#define MAX_TS UINT32_MAX
24#else
25#define MAX_TS UINT64_MAX
26#endif
27
dp-arm66abfbe2017-01-31 13:01:04 +000028/* Following are used as ID's to capture time-stamp */
29#define PSCI_STAT_ID_ENTER_LOW_PWR 0
30#define PSCI_STAT_ID_EXIT_LOW_PWR 1
31#define PSCI_STAT_TOTAL_IDS 2
32
33PMF_REGISTER_SERVICE(psci_svc, PMF_PSCI_STAT_SVC_ID, PSCI_STAT_TOTAL_IDS,
34 PMF_STORE_ENABLE)
35
36/*
37 * This function calculates the stats residency in microseconds,
38 * taking in account the wrap around condition.
39 */
40static u_register_t calc_stat_residency(unsigned long long pwrupts,
41 unsigned long long pwrdnts)
42{
43 /* The divisor to use to convert raw timestamp into microseconds. */
44 u_register_t residency_div;
45 u_register_t res;
46
47 /*
48 * Calculate divisor so that it can be directly used to
49 * convert time-stamp into microseconds.
50 */
51 residency_div = read_cntfrq_el0() / MHZ_TICKS_PER_SEC;
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010052 assert(residency_div > 0U);
dp-arm66abfbe2017-01-31 13:01:04 +000053
54 if (pwrupts < pwrdnts)
Soby Mathew8336f682017-10-16 15:19:31 +010055 res = MAX_TS - pwrdnts + pwrupts;
dp-arm66abfbe2017-01-31 13:01:04 +000056 else
57 res = pwrupts - pwrdnts;
58
59 return res / residency_div;
60}
61
62/*
63 * Capture timestamp before entering a low power state.
64 * No cache maintenance is required when capturing the timestamp.
65 * Cache maintenance may be needed when reading these timestamps.
66 */
67void plat_psci_stat_accounting_start(
68 __unused const psci_power_state_t *state_info)
69{
Antonio Nino Diazfec756f2018-07-18 16:24:16 +010070 assert(state_info != NULL);
dp-arm66abfbe2017-01-31 13:01:04 +000071 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR,
72 PMF_NO_CACHE_MAINT);
73}
74
75/*
76 * Capture timestamp after exiting a low power state.
77 * No cache maintenance is required when capturing the timestamp.
78 * Cache maintenance may be needed when reading these timestamps.
79 */
80void plat_psci_stat_accounting_stop(
81 __unused const psci_power_state_t *state_info)
82{
Antonio Nino Diazfec756f2018-07-18 16:24:16 +010083 assert(state_info != NULL);
dp-arm66abfbe2017-01-31 13:01:04 +000084 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR,
85 PMF_NO_CACHE_MAINT);
86}
87
88/*
89 * Calculate the residency for the given level and power state
90 * information.
91 */
92u_register_t plat_psci_stat_get_residency(unsigned int lvl,
93 const psci_power_state_t *state_info,
94 int last_cpu_idx)
95{
96 plat_local_state_t state;
97 unsigned long long pwrup_ts = 0, pwrdn_ts = 0;
98 unsigned int pmf_flags;
99
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100100 assert((lvl >= PSCI_CPU_PWR_LVL) && (lvl <= PLAT_MAX_PWR_LVL));
101 assert(state_info != NULL);
102 assert(last_cpu_idx <= PLATFORM_CORE_COUNT);
dp-arm66abfbe2017-01-31 13:01:04 +0000103
104 if (lvl == PSCI_CPU_PWR_LVL)
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100105 assert((unsigned int)last_cpu_idx == plat_my_core_pos());
dp-arm66abfbe2017-01-31 13:01:04 +0000106
107 /*
108 * If power down is requested, then timestamp capture will
109 * be with caches OFF. Hence we have to do cache maintenance
110 * when reading the timestamp.
111 */
112 state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL];
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100113 if (is_local_state_off(state) != 0) {
dp-arm66abfbe2017-01-31 13:01:04 +0000114 pmf_flags = PMF_CACHE_MAINT;
115 } else {
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100116 assert(is_local_state_retn(state) == 1);
dp-arm66abfbe2017-01-31 13:01:04 +0000117 pmf_flags = PMF_NO_CACHE_MAINT;
118 }
119
120 PMF_GET_TIMESTAMP_BY_INDEX(psci_svc,
121 PSCI_STAT_ID_ENTER_LOW_PWR,
122 last_cpu_idx,
123 pmf_flags,
124 pwrdn_ts);
125
126 PMF_GET_TIMESTAMP_BY_INDEX(psci_svc,
127 PSCI_STAT_ID_EXIT_LOW_PWR,
128 plat_my_core_pos(),
129 pmf_flags,
130 pwrup_ts);
131
132 return calc_stat_residency(pwrup_ts, pwrdn_ts);
133}
134#endif /* ENABLE_PSCI_STAT && ENABLE_PMF */
135
Soby Mathew0d786072016-03-24 16:56:29 +0000136/*
137 * The PSCI generic code uses this API to let the platform participate in state
138 * coordination during a power management operation. It compares the platform
139 * specific local power states requested by each cpu for a given power domain
140 * and returns the coordinated target power state that the domain should
141 * enter. A platform assigns a number to a local power state. This default
142 * implementation assumes that the platform assigns these numbers in order of
143 * increasing depth of the power state i.e. for two power states X & Y, if X < Y
144 * then X represents a shallower power state than Y. As a result, the
145 * coordinated target local power state for a power domain will be the minimum
146 * of the requested local power states.
147 */
148plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
149 const plat_local_state_t *states,
150 unsigned int ncpu)
151{
152 plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100153 const plat_local_state_t *st = states;
154 unsigned int n = ncpu;
Soby Mathew0d786072016-03-24 16:56:29 +0000155
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100156 assert(ncpu > 0U);
Soby Mathew0d786072016-03-24 16:56:29 +0000157
158 do {
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100159 temp = *st;
160 st++;
Soby Mathew0d786072016-03-24 16:56:29 +0000161 if (temp < target)
162 target = temp;
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100163 n--;
164 } while (n > 0U);
Soby Mathew0d786072016-03-24 16:56:29 +0000165
166 return target;
167}