blob: 21bd34e0bd72e02aa0e238a0593f64b089a384e7 [file] [log] [blame]
Yann Gautier66386952018-07-05 16:49:51 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/pinctrl/stm32-pinfunc.h>
8/ {
9 soc {
10 pinctrl: pin-controller {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges = <0 0x50002000 0xa400>;
14 pins-are-numbered;
15
16 gpioa: gpio@50002000 {
17 gpio-controller;
18 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
21 reg = <0x0 0x400>;
22 clocks = <&rcc GPIOA>;
23 st,bank-name = "GPIOA";
24 status = "disabled";
25 };
26
27 gpiob: gpio@50003000 {
28 gpio-controller;
29 #gpio-cells = <2>;
30 interrupt-controller;
31 #interrupt-cells = <2>;
32 reg = <0x1000 0x400>;
33 clocks = <&rcc GPIOB>;
34 st,bank-name = "GPIOB";
35 status = "disabled";
36 };
37
38 gpioc: gpio@50004000 {
39 gpio-controller;
40 #gpio-cells = <2>;
41 interrupt-controller;
42 #interrupt-cells = <2>;
43 reg = <0x2000 0x400>;
44 clocks = <&rcc GPIOC>;
45 st,bank-name = "GPIOC";
46 status = "disabled";
47 };
48
49 gpiod: gpio@50005000 {
50 gpio-controller;
51 #gpio-cells = <2>;
52 interrupt-controller;
53 #interrupt-cells = <2>;
54 reg = <0x3000 0x400>;
55 clocks = <&rcc GPIOD>;
56 st,bank-name = "GPIOD";
57 status = "disabled";
58 };
59
60 gpioe: gpio@50006000 {
61 gpio-controller;
62 #gpio-cells = <2>;
63 interrupt-controller;
64 #interrupt-cells = <2>;
65 reg = <0x4000 0x400>;
66 clocks = <&rcc GPIOE>;
67 st,bank-name = "GPIOE";
68 status = "disabled";
69 };
70
71 gpiof: gpio@50007000 {
72 gpio-controller;
73 #gpio-cells = <2>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
76 reg = <0x5000 0x400>;
77 clocks = <&rcc GPIOF>;
78 st,bank-name = "GPIOF";
79 status = "disabled";
80 };
81
82 gpiog: gpio@50008000 {
83 gpio-controller;
84 #gpio-cells = <2>;
85 interrupt-controller;
86 #interrupt-cells = <2>;
87 reg = <0x6000 0x400>;
88 clocks = <&rcc GPIOG>;
89 st,bank-name = "GPIOG";
90 status = "disabled";
91 };
92
93 gpioh: gpio@50009000 {
94 gpio-controller;
95 #gpio-cells = <2>;
96 interrupt-controller;
97 #interrupt-cells = <2>;
98 reg = <0x7000 0x400>;
99 clocks = <&rcc GPIOH>;
100 st,bank-name = "GPIOH";
101 status = "disabled";
102 };
103
104 gpioi: gpio@5000a000 {
105 gpio-controller;
106 #gpio-cells = <2>;
107 interrupt-controller;
108 #interrupt-cells = <2>;
109 reg = <0x8000 0x400>;
110 clocks = <&rcc GPIOI>;
111 st,bank-name = "GPIOI";
112 status = "disabled";
113 };
114
115 gpioj: gpio@5000b000 {
116 gpio-controller;
117 #gpio-cells = <2>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 reg = <0x9000 0x400>;
121 clocks = <&rcc GPIOJ>;
122 st,bank-name = "GPIOJ";
123 status = "disabled";
124 };
125
126 gpiok: gpio@5000c000 {
127 gpio-controller;
128 #gpio-cells = <2>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
131 reg = <0xa000 0x400>;
132 clocks = <&rcc GPIOK>;
133 st,bank-name = "GPIOK";
134 status = "disabled";
135 };
136
137 uart4_pins_a: uart4@0 {
138 pins1 {
139 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
140 bias-disable;
141 drive-push-pull;
142 slew-rate = <0>;
143 };
144 pins2 {
145 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
146 bias-disable;
147 };
148 };
149
150 usart3_pins_a: usart3@0 {
151 pins1 {
152 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
153 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
154 bias-disable;
155 drive-push-pull;
156 slew-rate = <0>;
157 };
158 pins2 {
159 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
160 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
161 bias-disable;
162 };
163 };
164
165 sdmmc1_b4_pins_a: sdmmc1-b4@0 {
166 pins {
167 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
168 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
169 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
170 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
171 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
172 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
173 slew-rate = <3>;
174 drive-push-pull;
175 bias-disable;
176 };
177 };
178
179 sdmmc1_dir_pins_a: sdmmc1-dir@0 {
180 pins1 {
181 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
182 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
183 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
184 slew-rate = <3>;
185 drive-push-pull;
186 bias-pull-up;
187 };
188 pins2{
189 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
190 bias-pull-up;
191 };
192 };
193
194 sdmmc2_b4_pins_a: sdmmc2-b4@0 {
195 pins {
196 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
197 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
198 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
199 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
200 <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
201 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
202 slew-rate = <3>;
203 drive-push-pull;
204 bias-pull-up;
205 };
206 };
207
208 sdmmc2_d47_pins_a: sdmmc2-d47@0 {
209 pins {
210 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
211 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
212 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
213 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
214 slew-rate = <3>;
215 drive-push-pull;
216 bias-pull-up;
217 };
218 };
219 };
220
221 pinctrl_z: pin-controller-z {
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges = <0 0x54004000 0x400>;
225 pins-are-numbered;
226
227 gpioz: gpio@54004000 {
228 gpio-controller;
229 #gpio-cells = <2>;
230 interrupt-controller;
231 #interrupt-cells = <2>;
232 reg = <0 0x400>;
233 clocks = <&rcc GPIOZ>;
234 st,bank-name = "GPIOZ";
235 st,bank-ioport = <11>;
236 status = "disabled";
237 };
238
239 i2c4_pins_a: i2c4@0 {
240 pins {
241 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
242 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
243 bias-disable;
244 drive-open-drain;
245 slew-rate = <0>;
246 };
247 };
248 };
249 };
250};