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Aditya Angadiaaa7b272020-11-19 17:32:41 +05301/*
Rohit Mathew9c07f602021-12-13 15:33:04 +00002 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
Aditya Angadiaaa7b272020-11-19 17:32:41 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8
9#include <platform_def.h>
10
11#include <plat/arm/common/plat_arm.h>
12#include <plat/common/platform.h>
13#include <drivers/arm/sbsa.h>
14
Omkar Anand Kulkarni2994dc02021-01-22 12:58:08 +053015#if SPM_MM
16#include <services/spm_mm_partition.h>
17#endif
18
Aditya Angadiaaa7b272020-11-19 17:32:41 +053019/*
20 * Table of regions for different BL stages to map using the MMU.
21 */
22#if IMAGE_BL1
23const mmap_region_t plat_arm_mmap[] = {
24 ARM_MAP_SHARED_RAM,
25 SGI_MAP_FLASH0_RO,
26 CSS_SGI_MAP_DEVICE,
27 SOC_PLATFORM_PERIPH_MAP_DEVICE,
28 SOC_SYSTEM_PERIPH_MAP_DEVICE,
29 {0}
30};
31#endif
32
33#if IMAGE_BL2
34const mmap_region_t plat_arm_mmap[] = {
35 ARM_MAP_SHARED_RAM,
36 SGI_MAP_FLASH0_RO,
37#ifdef PLAT_ARM_MEM_PROT_ADDR
38 ARM_V2M_MAP_MEM_PROTECT,
39#endif
40 CSS_SGI_MAP_DEVICE,
41 SOC_MEMCNTRL_MAP_DEVICE,
42 SOC_PLATFORM_PERIPH_MAP_DEVICE,
43 SOC_SYSTEM_PERIPH_MAP_DEVICE,
44 ARM_MAP_NS_DRAM1,
Aditya Angadiccae8a12021-08-09 09:38:58 +053045#if CSS_SGI_CHIP_COUNT > 1
46 SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(1),
47#endif
48#if CSS_SGI_CHIP_COUNT > 2
49 SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(2),
50#endif
51#if CSS_SGI_CHIP_COUNT > 3
52 SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(3),
53#endif
Aditya Angadiaaa7b272020-11-19 17:32:41 +053054#if ARM_BL31_IN_DRAM
55 ARM_MAP_BL31_SEC_DRAM,
56#endif
Omkar Anand Kulkarni2994dc02021-01-22 12:58:08 +053057#if SPM_MM
58 ARM_SP_IMAGE_MMAP,
59#endif
Aditya Angadiaaa7b272020-11-19 17:32:41 +053060#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
61 ARM_MAP_BL1_RW,
62#endif
63 {0}
64};
65#endif
66
67#if IMAGE_BL31
68const mmap_region_t plat_arm_mmap[] = {
69 ARM_MAP_SHARED_RAM,
70#ifdef PLAT_ARM_MEM_PROT_ADDR
71 ARM_V2M_MAP_MEM_PROTECT,
72#endif
73 CSS_SGI_MAP_DEVICE,
74 SOC_PLATFORM_PERIPH_MAP_DEVICE,
75 SOC_SYSTEM_PERIPH_MAP_DEVICE,
Omkar Anand Kulkarni2994dc02021-01-22 12:58:08 +053076#if SPM_MM
77 ARM_SPM_BUF_EL3_MMAP,
78#endif
Aditya Angadiaaa7b272020-11-19 17:32:41 +053079 {0}
80};
81
Omkar Anand Kulkarni2994dc02021-01-22 12:58:08 +053082#if SPM_MM && defined(IMAGE_BL31)
83const mmap_region_t plat_arm_secure_partition_mmap[] = {
84 PLAT_ARM_SECURE_MAP_SYSTEMREG,
85 PLAT_ARM_SECURE_MAP_NOR2,
Rohit Mathew9c07f602021-12-13 15:33:04 +000086 SOC_PLATFORM_SECURE_UART,
Omkar Anand Kulkarni2994dc02021-01-22 12:58:08 +053087 SOC_PLATFORM_PERIPH_MAP_DEVICE_USER,
88 ARM_SP_IMAGE_MMAP,
89 ARM_SP_IMAGE_NS_BUF_MMAP,
90 ARM_SP_IMAGE_RW_MMAP,
91 ARM_SPM_BUF_EL0_MMAP,
92 {0}
93};
94#endif /* SPM_MM && defined(IMAGE_BL31) */
Aditya Angadiaaa7b272020-11-19 17:32:41 +053095#endif
96
97ARM_CASSERT_MMAP
98
Omkar Anand Kulkarni2994dc02021-01-22 12:58:08 +053099#if SPM_MM && defined(IMAGE_BL31)
100/*
101 * Boot information passed to a secure partition during initialisation. Linear
102 * indices in MP information will be filled at runtime.
103 */
104static spm_mm_mp_info_t sp_mp_info[] = {
105 [0] = {0x81000000, 0},
106 [1] = {0x81010000, 0},
107 [2] = {0x81020000, 0},
108 [3] = {0x81030000, 0},
109 [4] = {0x81040000, 0},
110 [5] = {0x81050000, 0},
111 [6] = {0x81060000, 0},
112 [7] = {0x81070000, 0},
113 [8] = {0x81080000, 0},
114 [9] = {0x81090000, 0},
115 [10] = {0x810a0000, 0},
116 [11] = {0x810b0000, 0},
117 [12] = {0x810c0000, 0},
118 [13] = {0x810d0000, 0},
119 [14] = {0x810e0000, 0},
120 [15] = {0x810f0000, 0},
121};
122
123const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
124 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
125 .h.version = VERSION_1,
126 .h.size = sizeof(spm_mm_boot_info_t),
127 .h.attr = 0,
128 .sp_mem_base = ARM_SP_IMAGE_BASE,
129 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
130 .sp_image_base = ARM_SP_IMAGE_BASE,
131 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
132 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
133 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
134 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
135 .sp_image_size = ARM_SP_IMAGE_SIZE,
136 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
137 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
138 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
139 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
140 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
141 .num_cpus = PLATFORM_CORE_COUNT,
142 .mp_info = &sp_mp_info[0],
143};
144
145const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
146{
147 return plat_arm_secure_partition_mmap;
148}
149
150const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
151 void *cookie)
152{
153 return &plat_arm_secure_partition_boot_info;
154}
155#endif /* SPM_MM && defined(IMAGE_BL31) */
156
Aditya Angadiaaa7b272020-11-19 17:32:41 +0530157#if TRUSTED_BOARD_BOOT
158int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
159{
160 assert(heap_addr != NULL);
161 assert(heap_size != NULL);
162
163 return arm_get_mbedtls_heap(heap_addr, heap_size);
164}
165#endif
166
167void plat_arm_secure_wdt_start(void)
168{
169 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
170}
171
172void plat_arm_secure_wdt_stop(void)
173{
174 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
175}