blob: 025255bdab0d22288602041c8d2bc4251762646a [file] [log] [blame]
Tejas Patel9d09ff92019-01-08 01:46:35 -08001/*
2 * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PM_API_SYS_H
8#define PM_API_SYS_H
9
10#include <stdint.h>
Tejas Patelfe0e10a2019-12-08 23:29:44 -080011#include "pm_defs.h"
Tejas Patel9d09ff92019-01-08 01:46:35 -080012
13/**********************************************************
14 * PM API function declarations
15 **********************************************************/
16
17enum pm_ret_status pm_get_api_version(unsigned int *version);
Tejas Patelfe0e10a2019-12-08 23:29:44 -080018enum pm_ret_status pm_self_suspend(uint32_t nid,
19 unsigned int latency,
20 unsigned int state,
21 uintptr_t address);
22enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason);
23enum pm_ret_status pm_req_suspend(uint32_t target,
24 uint8_t ack,
25 unsigned int latency,
26 unsigned int state);
Tejas Patel41f3e0b2019-01-08 01:46:37 -080027enum pm_ret_status pm_request_device(uint32_t device_id, uint32_t capabilities,
28 uint32_t qos, uint32_t ack);
29enum pm_ret_status pm_release_device(uint32_t device_id);
30enum pm_ret_status pm_set_requirement(uint32_t device_id, uint32_t capabilities,
31 uint32_t latency, uint32_t qos);
32enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response);
Tejas Patel87c4f3a2019-01-08 01:46:38 -080033enum pm_ret_status pm_reset_assert(uint32_t reset, bool assert);
34enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status);
Tejas Patel20e92022019-01-08 01:46:39 -080035enum pm_ret_status pm_pinctrl_request(uint32_t pin);
36enum pm_ret_status pm_pinctrl_release(uint32_t pin);
37enum pm_ret_status pm_pinctrl_set_function(uint32_t pin, uint32_t function);
38enum pm_ret_status pm_pinctrl_get_function(uint32_t pin, uint32_t *function);
39enum pm_ret_status pm_pinctrl_set_pin_param(uint32_t pin, uint32_t param,
40 uint32_t value);
41enum pm_ret_status pm_pinctrl_get_pin_param(uint32_t pin, uint32_t param,
42 uint32_t *value);
Tejas Patel1f56fb12019-01-08 01:46:40 -080043enum pm_ret_status pm_clock_enable(uint32_t clk_id);
44enum pm_ret_status pm_clock_disable(uint32_t clk_id);
45enum pm_ret_status pm_clock_get_state(uint32_t clk_id, uint32_t *state);
46enum pm_ret_status pm_clock_set_divider(uint32_t clk_id, uint32_t divider);
47enum pm_ret_status pm_clock_get_divider(uint32_t clk_id, uint32_t *divider);
48enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent);
49enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent);
Tejas Patel023116d2019-01-08 01:46:41 -080050enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param,
51 uint32_t value);
52enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param,
53 uint32_t *value);
54enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode);
55enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode);
Tejas Patel9d09ff92019-01-08 01:46:35 -080056
57#endif /* PM_API_SYS_H */