Jiafei Pan | 46367ad | 2018-03-02 07:23:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Jiafei Pan | 46367ad | 2018-03-02 07:23:30 +0000 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <drivers/arm/tzc400.h> |
| 11 | #include <lib/utils.h> |
| 12 | #include <plat/common/common_def.h> |
| 13 | |
Jiafei Pan | 46367ad | 2018-03-02 07:23:30 +0000 | [diff] [blame] | 14 | #include "ls_def.h" |
| 15 | |
| 16 | #define FIRMWARE_WELCOME_STR_LS1043 "Welcome to LS1043 BL1 Phase\n" |
| 17 | #define FIRMWARE_WELCOME_STR_LS1043_BL2 "Welcome to LS1043 BL2 Phase\n" |
| 18 | #define FIRMWARE_WELCOME_STR_LS1043_BL31 "Welcome to LS1043 BL31 Phase\n" |
| 19 | #define FIRMWARE_WELCOME_STR_LS1043_BL32 "Welcome to LS1043 BL32 Phase, TSP\n" |
| 20 | |
| 21 | /* Required platform porting definitions */ |
| 22 | #define PLAT_PRIMARY_CPU 0x0 |
| 23 | #define PLAT_MAX_PWR_LVL LS_PWR_LVL1 |
| 24 | #define PLATFORM_CORE_COUNT 4 |
| 25 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ |
| 26 | |
| 27 | /* |
| 28 | * Required LS standard platform porting definitions |
| 29 | */ |
| 30 | #define PLAT_LS_CLUSTER_COUNT 1 |
| 31 | #define PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 32 | #define LS1043_CLUSTER_COUNT 1 |
| 33 | #define LS1043_MAX_CPUS_PER_CLUSTER 4 |
| 34 | |
| 35 | #define LS_DRAM1_BASE 0x80000000 |
| 36 | #define LS_DRAM2_BASE 0x880000000 |
| 37 | #define LS_DRAM2_SIZE 0x780000000 /* 30G */ |
| 38 | #define LS_DRAM1_SIZE 0x80000000 /* 2G */ |
| 39 | #define LS_NS_DRAM_BASE LS_DRAM1_BASE |
| 40 | /* 64M Secure Memory, in fact there a 2M non-secure hole on top of it */ |
| 41 | #define LS_SECURE_DRAM_SIZE (64 * 1024 * 1024) |
| 42 | #define LS_SECURE_DRAM_BASE (LS_NS_DRAM_BASE + LS_DRAM1_SIZE - \ |
| 43 | LS_SECURE_DRAM_SIZE) |
| 44 | #define LS_NS_DRAM_SIZE (LS_DRAM1_SIZE - LS_SECURE_DRAM_SIZE) |
| 45 | |
| 46 | /* |
| 47 | * By default, BL2 is in DDR memory. |
| 48 | * If LS_BL2_IN_OCRAM is defined, BL2 will in OCRAM |
| 49 | */ |
| 50 | /* #define LS_BL2_IN_OCRAM */ |
| 51 | |
| 52 | #ifndef LS_BL2_IN_OCRAM |
| 53 | /* |
| 54 | * on top of SECURE memory is 2M non-secure hole for OPTee, |
| 55 | * 1M secure memory below this hole will be used for BL2. |
| 56 | */ |
| 57 | #define LS_BL2_DDR_BASE (LS_SECURE_DRAM_BASE + \ |
| 58 | LS_SECURE_DRAM_SIZE \ |
| 59 | - 3 * 1024 * 1024) |
| 60 | #endif |
| 61 | |
| 62 | #define PLAT_LS_CCSR_BASE 0x1000000 |
| 63 | #define PLAT_LS_CCSR_SIZE 0xF000000 |
| 64 | |
| 65 | /* Flash base address, currently ROM is not used for TF-A images on LS platforms */ |
| 66 | #define PLAT_LS_TRUSTED_ROM_BASE 0x60100000 |
| 67 | #define PLAT_LS_TRUSTED_ROM_SIZE 0x20000000 /* Flash size */ |
| 68 | #define PLAT_LS_FLASH_SIZE 0x20000000 |
| 69 | #define PLAT_LS_FLASH_BASE 0x60000000 |
| 70 | |
| 71 | #define LS_SRAM_BASE 0x10000000 |
| 72 | #define LS_SRAM_LIMIT 0x10020000 /* 128K */ |
| 73 | #define LS_SRAM_SHARED_SIZE 0x1000 /* 4K */ |
| 74 | #define LS_SRAM_SIZE (LS_SRAM_LIMIT - LS_SRAM_BASE) |
| 75 | #define LS_BL_RAM_BASE (LS_SRAM_BASE + LS_SRAM_SHARED_SIZE) |
| 76 | |
| 77 | #define PLAT_LS_FIP_MAX_SIZE 0x4000000 |
| 78 | |
| 79 | /* Memory Layout */ |
| 80 | |
| 81 | #define BL1_RO_BASE PLAT_LS_TRUSTED_ROM_BASE |
| 82 | #define BL1_RO_LIMIT (PLAT_LS_TRUSTED_ROM_BASE \ |
| 83 | + PLAT_LS_TRUSTED_ROM_SIZE) |
| 84 | #define PLAT_LS_FIP_BASE 0x60120000 |
| 85 | |
| 86 | #ifdef LS_BL2_IN_OCRAM |
| 87 | /* BL2 is in OCRAM */ |
| 88 | #define PLAT_LS_MAX_BL1_RW_SIZE (52 * 1024) /* 52K */ |
| 89 | #define PLAT_LS_MAX_BL31_SIZE (64 * 1024) /* 64K */ |
| 90 | #define PLAT_LS_MAX_BL2_SIZE (44 * 1024) /* 44K */ |
| 91 | /* Reserve memory in OCRAM for BL31 Text and ROData segment */ |
| 92 | #define BL31_TEXT_RODATA_SIZE (32 * 1024) /* 32K */ |
| 93 | #else /* LS_BL2_IN_OCRAM */ |
| 94 | /* BL2 in DDR */ |
| 95 | #define PLAT_LS_MAX_BL1_RW_SIZE (64 * 1024) /* 64K */ |
| 96 | #define PLAT_LS_MAX_BL31_SIZE (64 * 1024) /* 64K */ |
| 97 | #define PLAT_LS_MAX_BL2_SIZE (1 * 1024 * 1024) /* 1M */ |
| 98 | #endif /* LS_BL2_IN_OCRAM */ |
| 99 | /* |
| 100 | * Put BL31 at the start of OCRAM. |
| 101 | */ |
| 102 | #define BL31_BASE LS_SRAM_BASE |
| 103 | #define BL31_LIMIT (LS_SRAM_BASE + PLAT_LS_MAX_BL31_SIZE) |
| 104 | |
| 105 | #ifdef LS_BL2_IN_OCRAM |
| 106 | /* |
| 107 | * BL2 follow BL31 Text and ROData region. |
| 108 | */ |
| 109 | #define BL2_BASE (BL31_BASE + BL31_TEXT_RODATA_SIZE) |
| 110 | #define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE) |
| 111 | |
| 112 | #else |
| 113 | /* |
| 114 | * BL2 in DDR memory. |
| 115 | */ |
| 116 | #define BL2_BASE LS_BL2_DDR_BASE |
| 117 | #define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE) |
| 118 | |
| 119 | #endif |
| 120 | |
| 121 | /* |
| 122 | * Put BL1 RW at the top of the Trusted SRAM. |
| 123 | */ |
| 124 | #ifdef LS_BL2_IN_OCRAM |
| 125 | #define BL1_RW_BASE BL2_LIMIT |
| 126 | #else |
| 127 | #define BL1_RW_BASE BL31_LIMIT |
| 128 | #endif |
| 129 | #define BL1_RW_LIMIT LS_SRAM_LIMIT |
| 130 | |
| 131 | /* Put BL32 in secure memory */ |
| 132 | #define BL32_BASE LS_SECURE_DRAM_BASE |
| 133 | #define BL32_LIMIT (LS_SECURE_DRAM_BASE + LS_SECURE_DRAM_SIZE) |
| 134 | /* BL33 memory region */ |
| 135 | #define BL33_BASE 0x82000000 |
| 136 | #define BL33_LIMIT (LS_NS_DRAM_BASE + LS_NS_DRAM_SIZE) |
| 137 | |
| 138 | /******************************************************************************* |
| 139 | * BL32 specific defines. |
| 140 | ******************************************************************************/ |
| 141 | /* |
| 142 | * On ARM standard platforms, the TSP can execute from Trusted SRAM, |
| 143 | * Trusted DRAM (if available) or the DRAM region secured by the TrustZone |
| 144 | * controller. |
| 145 | */ |
| 146 | |
| 147 | #define TSP_SEC_MEM_BASE BL32_BASE |
| 148 | #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) |
| 149 | |
| 150 | /* |
| 151 | * ID of the secure physical generic timer interrupt used by the TSP. |
| 152 | */ |
| 153 | #define TSP_IRQ_SEC_PHY_TIMER 29 |
| 154 | |
| 155 | |
| 156 | /* |
| 157 | * GIC related constants |
| 158 | */ |
| 159 | #define PLAT_LS1043_CCI_BASE 0x01180000 |
| 160 | #define GICD_BASE 0x01401000 |
| 161 | #define GICC_BASE 0x01402000 |
| 162 | #define GICD_BASE_64K 0x01410000 |
| 163 | #define GICC_BASE_64K 0x01420000 |
| 164 | |
| 165 | #define DCFG_CCSR_SVR 0x1ee00a4 |
| 166 | #define REV1_0 0x10 |
| 167 | #define REV1_1 0x11 |
| 168 | #define GIC_ADDR_BIT 31 |
| 169 | #define SCFG_GIC400_ALIGN 0x1570188 |
| 170 | |
| 171 | /* UART related definition */ |
| 172 | |
| 173 | #define PLAT_LS1043_DUART1_BASE 0x021c0000 |
| 174 | #define PLAT_LS1043_DUART2_BASE 0x021d0000 |
| 175 | #define PLAT_LS1043_DUART_SIZE 0x10000 |
| 176 | |
| 177 | #define PLAT_LS1043_UART_BASE 0x21c0500 |
| 178 | #define PLAT_LS1043_UART2_BASE 0x21c0600 |
| 179 | #define PLAT_LS1043_UART_CLOCK 400000000 |
| 180 | #define PLAT_LS1043_UART_BAUDRATE 115200 |
| 181 | /* Define UART to be used by TF-A log */ |
| 182 | #define LS_TF_UART_BASE PLAT_LS1043_UART_BASE |
| 183 | #define LS_TF_UART_CLOCK PLAT_LS1043_UART_CLOCK |
| 184 | #define LS_TF_UART_BAUDRATE PLAT_LS1043_UART_BAUDRATE |
| 185 | |
| 186 | #define LS1043_SYS_CNTCTL_BASE 0x2B00000 |
| 187 | |
| 188 | #define CONFIG_SYS_IMMR 0x01000000 |
| 189 | #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) |
| 190 | |
| 191 | /* Size of cacheable stacks */ |
| 192 | #if defined(IMAGE_BL1) |
| 193 | #define PLATFORM_STACK_SIZE 0x440 |
| 194 | #define MAX_MMAP_REGIONS 6 |
| 195 | #define MAX_XLAT_TABLES 4 |
| 196 | #elif defined(IMAGE_BL2) |
| 197 | #define PLATFORM_STACK_SIZE 0x400 |
| 198 | #define MAX_MMAP_REGIONS 8 |
| 199 | #define MAX_XLAT_TABLES 6 |
| 200 | #elif defined(IMAGE_BL31) |
| 201 | #define PLATFORM_STACK_SIZE 0x400 |
| 202 | #define MAX_MMAP_REGIONS 8 |
| 203 | #define MAX_XLAT_TABLES 4 |
| 204 | #elif defined(IMAGE_BL32) |
| 205 | #define PLATFORM_STACK_SIZE 0x440 |
| 206 | #define MAX_MMAP_REGIONS 8 |
| 207 | #define MAX_XLAT_TABLES 9 |
| 208 | #endif |
| 209 | |
| 210 | #define MAX_IO_DEVICES 3 |
| 211 | #define MAX_IO_HANDLES 4 |
| 212 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 213 | #endif /* PLATFORM_DEF_H */ |