blob: 5fd965520e4cb33c2670fe66e8d5db16c1e411eb [file] [log] [blame]
Nariman Poushinc703f902018-03-07 10:29:57 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/bl_common.h>
8#include <common/debug.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +00009#include <plat/arm/common/plat_arm.h>
10#include <plat/arm/soc/common/soc_css.h>
Aditya Angadi20b48412019-04-16 11:29:14 +053011#include <plat/arm/common/arm_def.h>
12#include <drivers/arm/sp805.h>
Nariman Poushinc703f902018-03-07 10:29:57 +000013#include <sgm_plat_config.h>
Nariman Poushinc703f902018-03-07 10:29:57 +000014
15void bl1_early_platform_setup(void)
16{
Nariman Poushinc703f902018-03-07 10:29:57 +000017
Girish Pathak66dd23c2018-10-02 15:18:34 +010018 /* Initialize the console before anything else */
Nariman Poushinc703f902018-03-07 10:29:57 +000019 arm_bl1_early_platform_setup();
20
Girish Pathak66dd23c2018-10-02 15:18:34 +010021 /* Initialize the platform configuration structure */
22 plat_config_init();
23
Nariman Poushinc703f902018-03-07 10:29:57 +000024#if !HW_ASSISTED_COHERENCY
25 /*
26 * Initialize Interconnect for this cluster during cold boot.
27 * No need for locks as no other CPU is active.
28 */
29 plat_arm_interconnect_init();
30 /*
31 * Enable Interconnect coherency for the primary CPU's cluster.
32 */
33 plat_arm_interconnect_enter_coherency();
34#endif
35}
Aditya Angadi20b48412019-04-16 11:29:14 +053036
37void plat_arm_secure_wdt_start(void)
38{
39 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
40}
41
42void plat_arm_secure_wdt_stop(void)
43{
44 sp805_stop(ARM_SP805_TWDG_BASE);
45}