Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 7 | #include <dram_regs.h> |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 8 | #include <m0_param.h> |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 9 | #include <pmu_bits.h> |
| 10 | #include <pmu_regs.h> |
| 11 | #include "misc_regs.h" |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 12 | #include "rk3399_mcu.h" |
| 13 | |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 14 | static uint32_t gatedis_con0; |
Lin Huang | 2510366 | 2016-12-30 11:50:01 +0800 | [diff] [blame] | 15 | |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 16 | static void idle_port(void) |
| 17 | { |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 18 | gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); |
| 19 | mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff); |
| 20 | |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 21 | mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 22 | (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 23 | while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 24 | ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) != |
| 25 | ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 26 | continue; |
| 27 | } |
| 28 | |
| 29 | static void deidle_port(void) |
| 30 | { |
| 31 | mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 32 | (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 33 | while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 34 | ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 35 | continue; |
Lin Huang | 2510366 | 2016-12-30 11:50:01 +0800 | [diff] [blame] | 36 | |
| 37 | /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 38 | mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 39 | } |
| 40 | |
| 41 | static void ddr_set_pll(void) |
| 42 | { |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 43 | mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 44 | |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 45 | mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); |
| 46 | mmio_write_32(CRU_BASE + CRU_DPLL_CON0, |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 47 | mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 48 | mmio_write_32(CRU_BASE + CRU_DPLL_CON1, |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 49 | mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 50 | mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 51 | |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 52 | while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 53 | continue; |
| 54 | |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 55 | mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 56 | } |
| 57 | |
Lin Huang | 00960ba | 2018-04-20 15:55:21 +0800 | [diff] [blame^] | 58 | __attribute__((noreturn)) void main(void) |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 59 | { |
Derek Basehore | 397046c | 2017-02-01 18:09:13 -0800 | [diff] [blame] | 60 | mmio_setbits_32(PHY_REG(0, 927), (1 << 22)); |
| 61 | mmio_setbits_32(PHY_REG(1, 927), (1 << 22)); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 62 | idle_port(); |
| 63 | |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 64 | mmio_write_32(CIC_BASE + CIC_CTRL0, |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 65 | (((0x3 << 4) | (1 << 2) | 1) << 16) | |
| 66 | (1 << 2) | 1 | |
| 67 | mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 68 | while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0) |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 69 | continue; |
| 70 | |
| 71 | ddr_set_pll(); |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 72 | mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002); |
| 73 | while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0) |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 74 | continue; |
| 75 | |
| 76 | deidle_port(); |
Derek Basehore | 397046c | 2017-02-01 18:09:13 -0800 | [diff] [blame] | 77 | mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); |
| 78 | mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); |
Lin Huang | 00960ba | 2018-04-20 15:55:21 +0800 | [diff] [blame^] | 79 | |
| 80 | mmio_write_32(PARAM_ADDR + PARAM_M0_DONE, M0_DONE_FLAG); |
| 81 | |
| 82 | for (;;) |
| 83 | __asm__ volatile ("wfi"); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 84 | } |